公开(公告)号：US20070105368A1

公开(公告)日：2007-05-10

申请号：US11268036

申请日：2005-11-07

Applicant: Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Haowen Bu ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/823807 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823864

Abstract: The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.

Abstract translation: 本发明在一个实施例中提供了一种制造微电子器件200的方法。 该实施例包括在衬底210和栅极结构230上形成衬垫310，使衬垫310经受电子束405并在衬垫310上沉积预金属介电层415。

公开(公告)号：US20070032094A1

公开(公告)日：2007-02-08

申请号：US11196985

申请日：2005-08-04

Applicant: Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

Inventor： Ting Tsui ,  Andrew McKerrow ,  Satyavolu Rao ,  Robert Kraft

IPC: H01L21/469

CPC classification number: H01L21/76825

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract translation: 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US20050196955A1

公开(公告)日：2005-09-08

申请号：US11114563

申请日：2005-04-25

Applicant: Ting Tsui ,  Andrew McKerrow ,  Jeannette Jacques

Inventor： Ting Tsui ,  Andrew McKerrow ,  Jeannette Jacques

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.

Abstract translation: 本发明提供了一种用于集成电路110的绝缘层100，其包括位于衬底130上方的多孔硅基电介质层120。 绝缘层包括致密层140，其包括多孔硅基电介质层的最上部分142。

公开(公告)号：US07678713B2

公开(公告)日：2010-03-16

申请号：US11196985

申请日：2005-08-04

Applicant: Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

Inventor： Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76825

Abstract: The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

Abstract translation: 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

公开(公告)号：US06872665B1

公开(公告)日：2005-03-29

申请号：US09599718

申请日：2000-06-22

Applicant: Francis G. Celii ,  Guoqiang Xing ,  Andrew McKerrow ,  Andrew Ralston ,  Zhicheng Tang ,  Kenneth J. Newton ,  Robert Kraft ,  Jeff West

Inventor： Francis G. Celii ,  Guoqiang Xing ,  Andrew McKerrow ,  Andrew Ralston ,  Zhicheng Tang ,  Kenneth J. Newton ,  Robert Kraft ,  Jeff West

IPC: H01L21/768 ,  H01L21/20

CPC classification number: H01L21/76808

Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

Abstract translation: 用于形成互连线和通孔的双镶嵌工艺流程，其中在沟槽蚀刻之前蚀刻至少部分通孔（116）。 使用低k材料如热固性有机聚合物用于ILD（106）和IMD（110）。 在至少部分通孔蚀刻之后，BARC（120）沉积在包括在通孔（116）中的结构上。 然后，对沟槽（126）进行图案化和蚀刻。 虽然在沟槽蚀刻期间去除了至少一些BARC（120）材料，但是通孔（116）的底部被保护。

公开(公告)号：US20050090087A1

公开(公告)日：2005-04-28

申请号：US10977433

申请日：2004-10-29

Applicant: Jiong-Ping Lu ,  Glenn Tessmer ,  Melissa Hewson ,  Donald Miles ,  Ralf Willecke ,  Andrew McKerrow ,  Brian Kirkpatrick ,  Clinton Montgomery

Inventor： Jiong-Ping Lu ,  Glenn Tessmer ,  Melissa Hewson ,  Donald Miles ,  Ralf Willecke ,  Andrew McKerrow ,  Brian Kirkpatrick ,  Clinton Montgomery

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L29/78 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/321 ,  H01L21/3211 ,  H01L21/76834 ,  H01L29/665

Abstract: A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel silicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

Abstract translation: 描述了在半导体集成电路器件中形成硅化镍和氮化硅结构的工艺。 通过用氮气钝化硅化镍表面，可以实现硅化镍和氮化硅之间的良好粘附。 可以通过用等离子体活化的氮物种处理硅化镍表面来进行钝化。 替代的钝化方法是用金属氮化物膜覆盖硅化镍，并将衬底加热至约500℃。另一种替代方法是在硅化镍顶部溅射沉积氮化硅。

公开(公告)号：US09816193B2

公开(公告)日：2017-11-14

申请号：US13324890

申请日：2011-12-13

Applicant: Kousik Ganesan ,  Tighe Spurlin ,  Jonathan D. Reid ,  Shantinath Ghongadi ,  Andrew McKerrow ,  James E. Duncan

Inventor： Kousik Ganesan ,  Tighe Spurlin ,  Jonathan D. Reid ,  Shantinath Ghongadi ,  Andrew McKerrow ,  James E. Duncan

IPC: C25D7/12 ,  C25D21/04 ,  C25D3/38 ,  C25D5/08 ,  C25D17/00 ,  C25D21/14 ,  C25D5/00

CPC classification number: C25D3/38 ,  C25D5/003 ,  C25D5/08 ,  C25D7/123 ,  C25D17/001 ,  C25D21/04 ,  C25D21/14

Abstract: Methods, systems, and apparatus for plating a metal onto a work piece with a plating solution having a low oxygen concentration are described. In one aspect, a method includes reducing an oxygen concentration of a plating solution. The plating solution includes about 100 parts per million or less of an accelerator. After reducing the oxygen concentration of the plating solution, a wafer substrate is contacted with the plating solution in a plating cell. The oxygen concentration of the plating solution in the plating cell is about 1 part per million or less. A metal is electroplated with the plating solution onto the wafer substrate in the plating cell. After electroplating the metal onto the wafer substrate, an oxidizing strength of the plating solution is increased.