公开(公告)号：US20070083846A1

公开(公告)日：2007-04-12

申请号：US11192254

申请日：2005-07-28

Applicant: Harry Chuang ,  Cheng-Cheng Kuo

Inventor： Harry Chuang ,  Cheng-Cheng Kuo

IPC: G06F17/50

CPC classification number: G03F1/36

Abstract: A method comprising dissecting a photomask pattern layout into a plurality of segments, each segment having at least one evaluation point, applying a rule-based MPC to the photomask pattern layout and generating a rule-based MPC result, and applying a model-based MPC to the plurality of segments of the photomask pattern layout and generating an MPC correction that is influenced by the rule-based MPC result.

Abstract translation: 一种方法，包括将光掩模图案布局解剖成多个段，每个段具有至少一个评估点，将基于规则的MPC应用到光掩模图案布局并生成基于规则的MPC结果，以及应用基于模型的MPC 到光掩模图案布局的多个段，并产生受基于规则的MPC结果影响的MPC校正。

公开(公告)号：US07701034B2

公开(公告)日：2010-04-20

申请号：US11281030

申请日：2005-11-17

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823437 ,  H01L21/823481 ,  Y10S438/926

Abstract: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.

Abstract translation: 本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。 该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。 在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。 假图形可以具有不均匀的间隔或不均匀的纵横比。 虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。 虚拟图案和有源区域之间的间隔可以小于约1500nm。

公开(公告)号：US20060163665A1

公开(公告)日：2006-07-27

申请号：US11281030

申请日：2005-11-17

Applicant: Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

Inventor： Harry Chuang ,  Kong-Beng Thei ,  Cheng-Cheng Kuo

IPC: H01L29/76

CPC classification number: H01L27/0207 ,  H01L21/823437 ,  H01L21/823481 ,  Y10S438/926

Abstract: An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.

Abstract translation: 本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。 该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。 在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。 假图形可以具有不均匀的间隔或不均匀的纵横比。 虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。 虚拟图案和有源区域之间的间隔可以小于约1500nm。

公开(公告)号：US09054025B2

公开(公告)日：2015-06-09

申请号：US12478135

申请日：2009-06-04

Applicant: Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

Inventor： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

IPC: H01L21/66 ,  H01L21/762

CPC classification number: H01L22/20 ,  H01L21/76224 ,  H01L22/12

Abstract: A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.

Abstract translation: 公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。 该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

公开(公告)号：US20120146057A1

公开(公告)日：2012-06-14

申请号：US13399394

申请日：2012-02-17

Applicant: Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L29/78 ,  H01L29/24

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

Abstract translation: 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

公开(公告)号：US08193586B2

公开(公告)日：2012-06-05

申请号：US12389535

申请日：2009-02-20

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

IPC: H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US08174091B2

公开(公告)日：2012-05-08

申请号：US12503641

申请日：2009-07-15

Applicant: Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

Inventor： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

Abstract translation: 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US08153498B2

公开(公告)日：2012-04-10

申请号：US12401876

申请日：2009-03-11

Applicant: Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

Inventor： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC: H01L21/8232

CPC classification number: H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

Abstract translation: 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

公开(公告)号：US08093120B2

公开(公告)日：2012-01-10

申请号：US12839994

申请日：2010-07-20

Applicant: Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

Inventor： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC: H01L21/8238

CPC classification number: H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

Abstract: A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Abstract translation: 提供了一种提供基板的方法， 在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。 示例性接触特征是双重接触。

公开(公告)号：US08035165B2

公开(公告)日：2011-10-11

申请号：US12341891

申请日：2008-12-22

Applicant: Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

Inventor： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

Abstract: A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

Abstract translation: 提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。 所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。