公开(公告)号：US06617661B2

公开(公告)日：2003-09-09

申请号：US09485915

申请日：2000-05-17

申请人： Hartmut Michel ,  Bernd Bireckoven ,  Dirk Hoheisel ,  Ning Qu

发明人： Hartmut Michel ,  Bernd Bireckoven ,  Dirk Hoheisel ,  Ning Qu

IPC分类号： H01L2900

CPC分类号： H01L29/87 ,  H01L27/04 ,  H01L29/0684

摘要： A high-voltage component and a method for its manufacture. The component functions to switch currents at high voltages. The component is composed of partial components that are connected in series and are laterally supported on a self-supporting semiconductor wafer. The partial components switch through, for example, at a given voltage applied between a first bridge cathode and an anodic metallization.

摘要翻译： 高压元件及其制造方法。 该组件用于在高电压下切换电流。 该部件由串联连接并横向支撑在自支撑半导体晶片上的部分部件组成。 部分组件例如通过施加在第一桥式阴极和阳极金属化之间的给定电压来切换。

公开(公告)号：US5780877A

公开(公告)日：1998-07-14

申请号：US795624

申请日：1997-02-06

申请人： Bernd Bireckoven ,  Dirk Hoheisel ,  Ning Qu

发明人： Bernd Bireckoven ,  Dirk Hoheisel ,  Ning Qu

IPC分类号： H01L29/74 ,  F02P7/03 ,  H01L31/111

CPC分类号： F02P7/035 ,  H01L31/1113

摘要： A break-over photodiode, designed as a light-sensitive thyristor, can be stacked using a series connection with a plurality of break-over photodiodes, such stacking representing a high-voltage break-over diode. The break-over photodiode can be triggered by lateral illumination in an edge zone, and includes a gate-layer resistivity under the emitter which is greater in an edge zone of the break-over photodiode than in the central zone of the break-over photodiode. The light sensitivity of the laterally illuminatable break-over photodiode is increased by a greater gate-layer resistivity in the edge zone as compared to the central zone.

摘要翻译： 设计为感光晶闸管的断路光电二极管可以使用与多个断开光电二极管的串联连接堆叠，这样堆叠代表高压断路二极管。 断路光电二极管可以通过边缘区域中的横向照明来触发，并且在发射极之下包括栅极层电阻率，其在断开光电二极管的边缘区域比在断开光电二极管的中心区域更大 。 与中心区域相比，侧向可照明的断开光电二极管的光敏度在边缘区域中增加了更大的栅极层电阻率。

公开(公告)号：US06597556B1

公开(公告)日：2003-07-22

申请号：US09424478

申请日：2000-06-01

申请人： Hartmut Michel ,  Christian Pluntke ,  Manfred Thanner ,  Bernd Bireckoven

发明人： Hartmut Michel ,  Christian Pluntke ,  Manfred Thanner ,  Bernd Bireckoven

IPC分类号： H02H504

CPC分类号： H03K17/16 ,  H03K17/0826 ,  H03K2017/0806

摘要： An integrated circuit having a power transistor and a circuit arrangement functioning in a temperature dependant manner and thermally coupled to the power transitor. The integrated circuit is used to reliably disconnect the power transistor in the event of overheating., particularly in the case of inductive loads, and does not reactivate the power transistor until, for example, an edge change has occurred at the base terminal of the integrated circuit.

摘要翻译： 一种具有功率晶体管和电路装置的集成电路，其以温度依赖的方式工作并热耦合到功率转换器。 集成电路用于在过热的情况下可靠地断开功率晶体管，特别是在感性负载的情况下，并且不会重新激活功率晶体管，直到例如在集成的基极端子上发生边缘变化 电路。

公开(公告)号：US5418411A

公开(公告)日：1995-05-23

申请号：US39214

申请日：1993-04-05

申请人： Hartmut Michel ,  Ulrich Nelle ,  Anton Mindl ,  Bernd Bireckoven

发明人： Hartmut Michel ,  Ulrich Nelle ,  Anton Mindl ,  Bernd Bireckoven

IPC分类号： H03G11/00 ,  H03K5/00 ,  H03B1/04

CPC分类号： H03G11/002

摘要： The invention relates to a voltage limiter for a transistor circuit with semiconductors (T.sub.20 and T.sub.21) in the arrangement of a plurality of successive amplifier stages, with a reference element (Zener diode Z.sub.20) and with at least one voltage divider arrangement (voltage divider R.sub.21 /R.sub.22). In accordance with the invention, the reference element (Zener diode Z.sub.20) is disposed downstream of the triggering circuit of the first stage or even closer at the output of the voltage limiter circuit for reducing the oscillation tendency.

摘要翻译： 本发明涉及一种用于具有半导体（T20和T21）的晶体管电路的电压限制器，其中多个连续放大器级具有参考元件（齐纳二极管Z20）和至少一个分压器装置（分压器R21 / R22）。 根据本发明，参考元件（齐纳二极管Z20）设置在第一级的触发电路的下游，或者甚至更靠近限流器电路的输出端，用于降低振荡趋势。

公开(公告)号：US06456108B1

公开(公告)日：2002-09-24

申请号：US09787796

申请日：2001-05-23

申请人： Helmut Schmied ,  Bernd Bireckoven ,  Hans Berkemer ,  Hartmut Michel

发明人： Helmut Schmied ,  Bernd Bireckoven ,  Hans Berkemer ,  Hartmut Michel

IPC分类号： H03K19003

CPC分类号： H03K17/22 ,  H03K17/16

摘要： Described is a control circuit for an output stage for suppressing electrical and electromagnetic interference having a signal input (I), a signal output (O), and a ground terminal, two switch stages (1; 2) which are connected to the signal input (I) and the ground and which have one control terminal and one output terminal each, each switch stage (1; 2) switching over from a first state in which the potential at the output terminal follows the potential at the signal input (I) to a second state in which the potential at the output terminal is drawn to ground when a first or second threshold value (Uin1, Uin2) is exceeded at its control terminal, the control terminal (4) of the first switch stage (1) being connected to an intermediary potential, which is between the potential at the signal input (I) and ground, the output terminal (5) of the first switch stage (1) forming the control terminal of the second switch stage (2), the output terminal of the second switch stage forming the signal output (O) of the control circuit, and the threshold value (Uin1) of the first switch stage being higher than the threshold value (Uin2) of the second switch stage.

摘要翻译： 描述了用于抑制具有信号输入（I），信号输出（O）和接地端子的电和电磁干扰的输出级的控制电路，两个开关级（1; 2）连接到信号输入端 （I）和地，并且具有一个控制端子和一个输出端子，每个开关级（1; 2）从输出端子上的电位跟随信号输入端（I）的电位的第一状态切换， 到第二状态，其中当在其控制端子超过第一或第二阈值（Uin1，Uin2）时，输出端子处的电位被拉到地，第一开关级（1）的控制端（4）为 连接到位于信号输入端（I）和地之间的电位之间的中间电位，形成第二开关级（2）的控制端的第一开关级（1）的输出端（5），输出端 端子形成第二开关台 N输出（O），第一开关级的阈值（Uin1）高于第二开关级的阈值（Uin2）。

公开(公告)号：US5841312A

公开(公告)日：1998-11-24

申请号：US669342

申请日：1996-07-01

申请人： Anton Mindl ,  Hartmut Michel ,  Bernd Bireckoven ,  Manfred Uebele ,  Ulrich Nelle

发明人： Anton Mindl ,  Hartmut Michel ,  Bernd Bireckoven ,  Manfred Uebele ,  Ulrich Nelle

IPC分类号： H02H7/20 ,  G05F1/56 ,  H03F1/30 ,  H03F1/52 ,  H03K17/08 ,  H03K17/082 ,  H03K17/14

CPC分类号： H03K17/0826 ,  H03K2017/0806

摘要： The gating circuit has a power transistor (T1, T2, T3) and a current measuring resistor (R5) connected with the power transistor so that a voltage drop at the measuring resistor is a measure of a current flow in the power transistor. This voltage drop is used to trigger a current regulating transistor (T5) and a temperature measuring transistor (T9). Below a predetermined temperature, the current flow is limited solely by the current regulating transistor (T5). Above this predetermined temperature the collector current is further reduced via the temperature measuring transistor (T9) and a further transistor (T10) so as to protect the power transistor from thermal overload.

摘要翻译： PCT No.PCT / DE95 / 00039 Sec。 371日期：1996年7月1日 102（e）日期1996年7月1日PCT提交1995年1月14日PCT公布。 WO95 / 20783 PCT出版物 日期1995年8月3日门电路具有与功率晶体管连接的功率晶体管（T1，T2，T3）和电流测量电阻（R5），使得测量电阻器处的电压降是测量电流 功率晶体管。 该电压降用于触发电流调节晶体管（T5）和温度测量晶体管（T9）。 低于预定温度，电流仅由电流调节晶体管（T5）限制。 在该预定温度之上，通过温度测量晶体管（T9）和另一个晶体管（T10）进一步减小集电极电流，以保护功率晶体管免受热过载。

公开(公告)号：US06697257B1

公开(公告)日：2004-02-24

申请号：US09857802

申请日：2002-04-09

申请人： Kuno Wolf ,  Gerhard Koelle ,  Juergen Zaremba ,  Wolfgang Jacob ,  Alexander Wallrauch ,  Christoph Ruf ,  Ralf Schmid ,  Peter Urbach ,  Bernd Bireckoven ,  Hans-Reiner Krauss ,  Dirk Scholz

发明人： Kuno Wolf ,  Gerhard Koelle ,  Juergen Zaremba ,  Wolfgang Jacob ,  Alexander Wallrauch ,  Christoph Ruf ,  Ralf Schmid ,  Peter Urbach ,  Bernd Bireckoven ,  Hans-Reiner Krauss ,  Dirk Scholz

IPC分类号： H05K720

CPC分类号： H01L25/071 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed in a power semiconductor module which includes a stack of carrier substrates, disposed one above the other in multiple layers and provided with at least one conductor track on at least one main surface, in which at least one electronic semiconductor component is disposed between two adjacent carrier substrates of the stack and is contacted electrically and heat-conductively to at least one conductor track of a carrier substrate disposed in the stack above the semiconductor component and to at least one further conductor track of a carrier substrate disposed in the stack below the semiconductor component. To both improve heat output and provide a compact design, the two outer carrier substrates of the stack are embodied as one upper and one lower housing wall of a closed housing part surrounding the at least one semiconductor component, and the interstices between the stacked carrier substrates are tightly closed by an encompassing wall secured to the carrier substrates.

摘要翻译： 公开在一种功率半导体模块中，该功率半导体模块包括一堆载体衬底，多个层叠在另一层之上并且在至少一个主表面上设置有至少一个导体轨道，其中至少一个电子半导体部件设置在两个相邻 并且对于布置在半导体部件上方的堆叠中的载体衬底的至少一个导体轨道和布置在半导体下面的堆叠中的载体衬底的至少一个另外的导体轨道，电性和热导电地接触 零件。 为了提高热输出并提供紧凑的设计，堆叠的两个外部载体衬底被实施为围绕至少一个半导体部件的封闭壳体部分的一个上部和一个下壳体壁，以及堆叠的载体衬底之间的间隙 被固定到载体基底的封闭壁紧密封闭。