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    MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WHOSE GATE INSULATING FILM CONTAINS Hf AND O
    1.
    发明申请
    MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WHOSE GATE INSULATING FILM CONTAINS Hf AND O 审中-公开
    门绝缘膜包含Hf和O的半导体器件的制造方法

    公开(公告)号：US20100178744A1

    公开(公告)日：2010-07-15

    申请号：US12646233

    申请日：2009-12-23

    申请人： Haruhiko Takahashi ,  Hiroshi Minakata ,  Naoyoshi Tamura

    发明人： Haruhiko Takahashi ,  Hiroshi Minakata ,  Naoyoshi Tamura

    IPC分类号： H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L29/4966

    摘要： An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film.

    摘要翻译： 在半导体衬底上形成具有Hf和O的绝缘膜。 在绝缘膜上形成具有氧和钛作为构成元件的盖膜。 绝缘膜和盖膜在氮气或惰性气体中进行热处理，以将帽膜中的钛扩散到绝缘膜中以形成栅极绝缘膜。 在栅极绝缘膜上形成栅极电极膜。

    Semiconductor device having high dielectric constant gate insulating layer and its manufacture method
    2.
    发明授权
    Semiconductor device having high dielectric constant gate insulating layer and its manufacture method 有权
    具有高介电常数栅极绝缘层的半导体器件及其制造方法

    公开(公告)号：US07265401B2

    公开(公告)日：2007-09-04

    申请号：US11148317

    申请日：2005-06-09

    申请人： Masaomi Yamaguchi ,  Hiroshi Minakata ,  Tsunehisa Sakoda ,  Kazuto Ikeda

    发明人： Masaomi Yamaguchi ,  Hiroshi Minakata ,  Tsunehisa Sakoda ,  Kazuto Ikeda

    IPC分类号： H01L29/94

    CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/513

    摘要： A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.

    摘要翻译： 半导体器件制造方法具有以下步骤：（a）在硅衬底的有源区的表面上形成SiO或SiON的界面层; （b）在界面层之上形成介电常数高于氧化硅的介电常数的诸如HfSiON的高介电常数栅极绝缘膜; （c）在高介电常数栅极绝缘膜上方形成多晶硅栅电极; （d）至少在形成高介电常数栅极绝缘膜之前或之后使基板表面钝化; （e）通过至少构图栅电极和高介电常数栅极绝缘膜来形成绝缘栅电极结构; 和（f）在绝缘栅电极结构两侧的有源区中形成源/漏区。 半导体器件具有介电常数比氧化硅高的介电常数绝缘膜。

    Method and apparatus for generating a free-form surface
    3.
    发明授权
    Method and apparatus for generating a free-form surface 失效
    用于产生自由曲面的方法和装置

    公开(公告)号：US5459821A

    公开(公告)日：1995-10-17

    申请号：US967467

    申请日：1992-10-23

    申请人： Shigeru Kuriyama ,  Hiroshi Minakata ,  Naoki Urano ,  Kazuya Shimizu

    发明人： Shigeru Kuriyama ,  Hiroshi Minakata ,  Naoki Urano ,  Kazuya Shimizu

    IPC分类号： B24B5/18 ,  B24B5/313 ,  G06T17/30 ,  G06T17/20

    CPC分类号： G06T17/30

    摘要： A method for generating a multisided patch in which the expression form of each boundary curve and topology of the curve network can freely be set, curve formulae can be simply input, and high continuity. By inputting data of boundary curves to multisided patch generator via editing means which generates and edits curves, and blending sweep surfaces in two stages, a free-form surface is generated as a surface interpolating them. That is, data of a plurality of boundary curves is inputted to multisided patch generator, each given curve is swept by sweeping means along the curves intersecting it to generate surfaces, and the surfaces are blended by blending means in two stages, thereby generating a free-form surface. Since the surface formulae can be defined on the basis of the curve formulae of the boundaries, topology of the curve network and the descriptive form of each curve can freely be set, so that the boundary curve formulae of a multisided patch can be simply input by directly drawing the curve shapes on defined two-dimensional planes. In addition, geometric continuity of the generated surface is high because continuity of the given curves is high.

    摘要翻译： 一种生成可以自由设置每个边界曲线的表达形式和曲线网络拓扑的多区块的方法，可以简单地输入曲线公式，并具有高连续性。 通过将生成和编辑曲线的编辑装置的边界曲线的数据输入到多段贴片发生器，并且将扫描表面混合在两个阶段中，生成自由曲面作为表面内插它们。 也就是说，多边界曲线的数据被输入到多片贴片发生器，每个给定的曲线被扫描装置沿着与其相交的曲线扫过以产生表面，并且表面通过混合装置分两个阶段共混，从而产生一个自由 形状表面。 由于表面公式可以根据边界的曲线公式定义，曲线网络的拓扑结构和每个曲线的描述形式可以自由设置，从而可以简单地输入多维贴片的边界曲线公式 直接在定义的二维平面上绘制曲线形状。 此外，由于给定曲线的连续性高，所以产生的表面的几何连续性很高。

    Semiconductor device and method for fabricating the same
    5.
    发明申请
    Semiconductor device and method for fabricating the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060214244A1

    公开(公告)日：2006-09-28

    申请号：US11198166

    申请日：2005-08-08

    申请人： Hiroshi Minakata

    发明人： Hiroshi Minakata

    IPC分类号： H01L29/78 ,  H01L21/4763

    CPC分类号： H01L21/31122 ,  H01L29/517 ,  H01L29/6659

    摘要： In the method for fabricating a semiconductor device, a polysilicon film is patterned to form a gate electrode 16, and a high dielectric constant insulating film 14 on a silicon substrate 10 and a device isolation film 12 on both sides of the gate electrode 16 is removed by dry etching using plasmas of a mixed gas of a base protection gas which combines with silicon to form a protection layer for protecting the silicon substrate 10 and the device isolation film 12, and an etching gas for etching the high dielectric constant insulating film 14.

    摘要翻译： 在制造半导体器件的方法中，对多晶硅膜进行构图以形成栅电极16，并且去除在硅衬底10上的高介电常数绝缘膜14和位于栅电极16两侧的器件隔离膜12 通过使用与硅组合的基底保护气体的混合气体的等离子体进行干蚀刻以形成用于保护硅衬底10和器件隔离膜12的保护层，以及用于蚀刻高介电常数绝缘膜14的蚀刻气体。

    Oxidizing a metal layer for a dielectric having a platinum electrode
    7.
    发明授权
    Oxidizing a metal layer for a dielectric having a platinum electrode 有权
    氧化具有铂电极的电介质的金属层

    公开(公告)号：US07470595B2

    公开(公告)日：2008-12-30

    申请号：US11497344

    申请日：2006-08-02

    申请人： Nobuyuki Nishikawa ,  Hiroshi Minakata ,  Kouji Tsunoda ,  Eiji Yoshida

    发明人： Nobuyuki Nishikawa ,  Hiroshi Minakata ,  Kouji Tsunoda ,  Eiji Yoshida

    IPC分类号： H01L21/20 ,  H01L21/76

    CPC分类号： H01L28/65 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

    摘要： A tight contact layer is disposed on a semiconductor substrate, the tight contact layer being made of one material selected from the group consisting of refractory metal, alloy of refractory metal, nitride of refractory metal, and siliconized nitride of refractory metal. An oxide surface layer is disposed on the surface of the tight contact layer, the oxide surface layer being made of oxide of material constituting the tight contact layer. A first conductive layer is disposed on the surface of the oxide surface layer, the first conductive layer being made of a platinum group or alloy which contains a platinum group. When a conductive layer made of metal such as a platinum group is formed on a tight contact layer, coverage and morphology can be prevented from being degraded.

    摘要翻译： 紧密接触层设置在半导体衬底上，紧密接触层由选自耐火金属，难熔金属合金，难熔金属氮化物和难熔金属的氮化硅组成的组中的一种材料制成。 氧化物表面层设置在紧密接触层的表面上，氧化物表面层由构成紧密接触层的材料的氧化物制成。 第一导电层设置在氧化物表面层的表面上，第一导电层由含有铂族的铂族或合金制成。 当在紧密接触层上形成由诸如铂族基团的金属制成的导电层时，可以防止覆盖和形态的劣​​化。

    Semiconductor device having high dielectric constant gate insulating layer and its manufacture method
    9.
    发明申请
    Semiconductor device having high dielectric constant gate insulating layer and its manufacture method 有权
    具有高介电常数栅极绝缘层的半导体器件及其制造方法

    公开(公告)号：US20060172498A1

    公开(公告)日：2006-08-03

    申请号：US11148317

    申请日：2005-06-09

    申请人： Masaomi Yamaguchi ,  Hiroshi Minakata ,  Tsunehisa Sakoda ,  Kazuto Ikeda

    发明人： Masaomi Yamaguchi ,  Hiroshi Minakata ,  Tsunehisa Sakoda ,  Kazuto Ikeda

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/3205

    CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/513

    摘要： A semiconductor device manufacture method has the steps of: (a) forming an interface layer of SiO or SiON on the surface of an active region of a silicon substrate; (b) forming a high dielectric constant gate insulating film such as HfSiON having a dielectric constant higher than that of silicon oxide, above the interface layer; (c) forming a gate electrode of polysilicon above the high dielectric constant gate insulating film; (d) passivating the substrate surface at least before or after the high dielectric constant gate insulating film is formed; (e) forming an insulated gate electrode structure by patterning at least the gate electrode and the high dielectric constant gate insulating film; and (f) forming source/drain regions in the active region on both sides of the insulated gate electrode structure. The semiconductor device has the high dielectric constant insulating film having a dielectric constant higher than that of silicon oxide.

    摘要翻译： 半导体器件制造方法具有以下步骤：（a）在硅衬底的有源区的表面上形成SiO或SiON的界面层; （b）在界面层之上形成介电常数高于氧化硅的介电常数的诸如HfSiON的高介电常数栅极绝缘膜; （c）在高介电常数栅极绝缘膜上方形成多晶硅栅电极; （d）至少在形成高介电常数栅极绝缘膜之前或之后使基板表面钝化; （e）通过至少构图栅电极和高介电常数栅极绝缘膜来形成绝缘栅电极结构; 和（f）在绝缘栅电极结构两侧的有源区中形成源/漏区。 半导体器件具有介电常数比氧化硅高的介电常数绝缘膜。