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公开(公告)号：US07426629B2
公开(公告)日：2008-09-16
申请号：US10527960
申请日：2003-10-06
CPC分类号： G06F9/30058 , G06F9/30189 , G06F9/3842 , G06F9/3861 , G06F9/3867 , G06F9/3875 , G06F21/71 , G06F21/75 , G06F21/755 , G06F2207/7219 , G06F2221/2123
摘要： A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.
摘要翻译： 数据处理系统具有这样的机制，即当数据值被存储在数据寄存器中时，另外的数据值存储在一个或多个另外的寄存器中，使得从高到低和从低到高的信号转换的总数量 不依赖于正在写入的数据值或先前的数据值而变化。
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公开(公告)号：US20100217937A1
公开(公告)日：2010-08-26
申请号：US12379440
申请日：2009-02-20
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/383 , G06F12/127 , G06F2212/6028
摘要： A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions. A cache controller is also provided which comprises preload circuitry operable in response to a streaming preload instruction received at the processor to store data values from a main memory into one or more cache lines of the cache memory. The cache controller also comprises identification circuitry operable in response to the streaming preload instruction to identify one or more cache lines of the cache memory for preferential reuse. The cache controller also comprises cache maintenance circuitry operable to implement a cache maintenance operation during which selection of one or more cache lines for reuse is performed having regard to any preferred for reuse identification generated by the identification circuitry for cache lines of the cache memory. In this way, a single streaming preload instruction can be used to trigger both a preload of one or more cache lines of data values into the cache memory, and also to mark for preferential reuse another one or more cache lines of the cache memory.
摘要翻译： 描述了一种数据处理装置，其包括可操作以执行指令序列的处理器和具有多个高速缓存行的高速缓存存储器，该多个高速缓存行可操作以在执行指令序列时存储用于由处理器访问的数据值。 还提供了一种缓存控制器，其包括预加载电路，该预加载电路响应于在处理器处接收到的流预加载指令而可操作以将来自主存储器的数据值存储到高速缓存存储器的一个或多个高速缓存行。 高速缓存控制器还包括可响应于流预加载指令操作的识别电路，以识别用于优先重用的高速缓冲存储器的一个或多个高速缓存行。 高速缓存控制器还包括可操作以实现高速缓存维护操作的高速缓存维护电路，在该高速缓存维护操作期间，考虑到用于高速缓冲存储器的高速缓存行的识别电路的识别电路产生的重用标识的任何优选，执行用于重新使用的一个或多个高速缓 以这种方式，可以使用单个流预加载指令来将数据值的一个或多个高速缓存行的预加载触发到高速缓冲存储器中，并且还用于标记用于优先重用高速缓冲存储器的另一个或多个高速缓存行。
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公开(公告)号：US06584532B1
公开(公告)日：2003-06-24
申请号：US09572729
申请日：2000-05-17
IPC分类号： G06F1326
CPC分类号： G06F13/26
摘要： A data processing system 2 for identifying the highest priority source signal from a plurality of signals each controlling the setting of a bit of a status word held within a status register 10 using programmable mask words. The mask words are used in a branch search strategy to successively narrow the possibilities for the highest priority bit at each search level until a single bit within the status word is identified corresponding to the highest priority interrupt signal. The programmable masks may be programmed for a particular configuration of the priorities of the respective bits within the status word. The branch search strategy provides a reduced maximum interrupt latency and improved predictability in the interrupt latency.
摘要翻译： 一种数据处理系统2，用于从多个信号中识别最高优先级的源信号，每个信号使用可编程掩码字来控制状态寄存器10中保持的状态字的位的设置。 在分支搜索策略中使用掩码字来连续地缩小每个搜索级别的最高优先级位的可能性，直到状态字中的单个位被识别为对应于最高优先级的中断信号。 可编程掩模可以被编程用于状态字内各个位的优先级的特定配置。 分支搜索策略提供了减少的最大中断延迟并提高了中断延迟的可预测性。
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4.发明授权公开(公告)号：US06831952B2
公开(公告)日：2004-12-14
申请号：US09799878
申请日：2001-03-07
IPC分类号： H04L2700
CPC分类号： G11B20/10296 , G11B20/12 , H03M13/39 , H03M13/41 , H03M13/4107
摘要： A technique for decoding an encoded data stream representing an original sequence of data bits, each data bit comprising a plurality of codes, each code being dependent on a current data bit and a first predetermined number of preceding data bits in the original sequence. Scores are provided indicating the likelihood that a corresponding state represents the first predetermined number of preceding data bits. The scores are arranged in an initial ordering. A first plurality of score bit slices are stored to collectively represent the initially ordered scores, each score bit slice containing a predetermined bit from each of the scores. The scores are then reordered and a second plurality of score bit slices are stored to collectively represent the reordered scores. By this approach, all the scores are updated simultaneously.
摘要翻译： 一种用于解码表示原始数据位序列的编码数据流的技术，每个数据位包括多个代码，每个代码取决于原始序列中的当前数据位和第一预定数量的先前数据位。 提供表示指示对应状态表示第一预定数量的先前数据位的可能性。 分数按初始排序排列。 存储第一多个分数比特片以共同表示最初排序的分数，每个分数比特片包含来自每个分数的预定比特。 然后重新排序分数，并且存储第二多个分数比特片以共同表示重新排序的分数。 通过这种方法，所有得分都被同时更新。
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公开(公告)号：US08010726B2
公开(公告)日：2011-08-30
申请号：US10788305
申请日：2004-03-01
申请人： Hedley James Francis
发明人： Hedley James Francis
CPC分类号： G06F13/26
摘要： A data processing apparatus and method for handling interrupts is provided, the apparatus having an interrupt controller operable to receive interrupts generated by a number of interrupt sources, and to determine based on predetermined criteria whether to output an interrupt request signal. A processing unit is provided which is operable upon receipt of the interrupt request signal to perform an interrupt service routine for a selected one of the received interrupts in order to generate an interrupt response for the corresponding interrupt source. Timer logic is also provided which is operable upon receipt of an interrupt generated by an associated interrupt source to produce a timing indication. As a result of this, the processing unit is operable, when performing the interrupt service routine for the interrupt generated by that associated interrupt source, to reference the timer logic in order to obtain the timing indication, and to control a predetermined aspect of the interrupt response in dependence on the timing indication. This has been found to provide a significantly improved technique for handling interrupts from interrupt sources which desire deterministic behavior with regards to the interrupt response.
摘要翻译： 提供一种用于处理中断的数据处理装置和方法，该装置具有可操作以接收由多个中断源产生的中断的中断控制器，并且基于是否输出中断请求信号来确定。 提供处理单元，其在接收到中断请求信号时可操作，以对所接收的中断中的所选中断执行中断服务程序，以便产生相应的中断源的中断响应。 还提供定时器逻辑，其可在接收到由相关联的中断源产生的中断以产生定时指示时操作。 因此，处理单元在执行由相关联的中断源产生的中断的中断服务程序时可以参考定时器逻辑以获得定时指示，并且控制中断的预定方面 响应时间指示。 已经发现，这提供了一种用于处理来自中断源的中断的显着改进的技术，其要求关于中断响应的确定性行为。
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6.发明授权Executing stack-based instructions within a data processing apparatus arranged to apply operations to data items stored in registers 有权在数据处理设备内执行基于堆栈的指令，该数据处理设备被布置为对存储在寄存器中的数据项进行操作公开(公告)号：US06978358B2
公开(公告)日：2005-12-20
申请号：US10113942
申请日：2002-04-02
申请人： Hedley James Francis
发明人： Hedley James Francis
CPC分类号： G06F9/3851 , G06F9/30134 , G06F9/30145 , G06F9/38
摘要： A data processor comprises a register bank containing a plurality of “n” bit registers for storing data items, a set of registers within the register bank being allocatable to hold stack data items from a portion of the stack, and each register in the set storing as an n-bit value stack data items of the first or second type. An arithmetic logic unit executes operations upon data items held in the registers and a decoder decodes a stack-based instruction to specify a number of operations to be executed by the arithmetic logic unit upon one or more stack data items held in predetermined registers in the set. Further, a stack controller is arranged to control movement of stack data items between the stack and the set of registers, and is responsive to the decoder causing one or more stack data items to be held in the predetermined registers.
摘要翻译： 数据处理器包括一个寄存器组，该寄存器组包含多个用于存储数据项的“n”位寄存器，寄存器组中的一组寄存器可分配以保存来自堆栈的一部分的堆栈数据项，存储器中的每个寄存器 作为n位值堆栈第一或第二类型的数据项。 算术逻辑单元对保存在寄存器中的数据项执行操作，并且解码器对基于堆栈的指令进行解码，以指定在保持在该组中的预定寄存器中的一个或多个堆栈数据项上由算术逻辑单元执行的操作的数量 。 此外，堆栈控制器被布置为控制堆栈和寄存器组之间的堆栈数据项的移动，并且响应于解码器使得一个或多个堆栈数据项保持在预定寄存器中。
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7.发明授权Executing variable length instructions stored within a plurality of discrete memory address regions 有权执行存储在多个离散存储器地址区域内的可变长度指令公开(公告)号：US07676652B2
公开(公告)日：2010-03-09
申请号：US10648293
申请日：2003-08-27
CPC分类号： G06F9/3816 , G06F9/30149 , G06F12/04
摘要： Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered. This execution is constrained by the setting of a single step flag which causes the hardware to only execute the single instruction which span the gap before returning control to a single step exception handler which can then restore program flow to the point in the following memory region after the variable length instruction which spanned the gap.
摘要翻译： 在支持执行可变长度指令的系统中，程序被存储在跨越两个这样的离散存储器区域之间的间隙的可变长度指令的离散存储器区域内。 当尝试跨越间隙的这种可变长度指令执行时，启动中止处理程序，其用于将其中一个存储器区域的端部与另一存储器区域的起始部分一起复制到单独的修正存储器区域 其中这些可以被级联，使得整个可变长度指令将出现在一个地方。 然后可以触发从固定存储区域中执行该可变长度指令。 该执行受到单步标志的设置的限制，这使得硬件仅在将控制返回到单步异常处理程序之前执行跨越间隙的单个指令，然后可以将程序流恢复到以下存储区域中的点 跨越差距的可变长度指令。
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公开(公告)号：US07627807B2
公开(公告)日：2009-12-01
申请号：US11114236
申请日：2005-04-26
CPC分类号： G06F11/366 , G06F11/0757 , G06F11/3471
摘要： Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic 22; wherein said detection logic is operable to detect a data or instruction access to at least one predetermined address and in response to not detecting said data or instruction access within said predetermined time, said control logic is operable to send a control signal to said data processor, said control signal controlling said data processor to perform a predetermined operation.
摘要翻译： 监控逻辑20，用于监视数据处理器10以检测其是否不按预期操作，监视逻辑20包括：定时器27，可操作以测量预定时间; 检测逻辑24; 和控制逻辑22; 其中所述检测逻辑可操作以检测对至少一个预定地址的数据或指令访问，并且响应于在所述预定时间内未检测到所述数据或指令访问，所述控制逻辑可操作以向所述数据处理器发送控制信号， 所述控制信号控制所述数据处理器执行预定的操作。
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公开(公告)号：US07802080B2
公开(公告)日：2010-09-21
申请号：US10807498
申请日：2004-03-24
申请人： David John Butcher , Stephen John Hill , Hedley James Francis , Vladimir Vasekin , Andrew Christopher Rose
发明人： David John Butcher , Stephen John Hill , Hedley James Francis , Vladimir Vasekin , Andrew Christopher Rose
CPC分类号： G06F9/3861 , G06F9/30174 , G06F9/355
摘要： A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.
摘要翻译： 处理器6设置有指令解码器18，该指令解码器18响应于存储器访问指令来确定正在使用的基本寄存器值是否与空值匹配，并且如果发生这样的匹配，则分支到空值异常处理程序。
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10.发明授权Data processing apparatus and method for merging secure and non-secure data into an output data stream 有权用于将安全和非安全数据合并到输出数据流中的数据处理装置和方法公开(公告)号：US07509502B2
公开(公告)日：2009-03-24
申请号：US10931210
申请日：2004-09-01
CPC分类号： G06F21/72 , G06F21/10 , G06F21/84 , G06F2221/0797 , G06F2221/2105
摘要： The present invention provides a data processing apparatus and method for merging secure and non-secure data. The apparatus comprises at least one processor operable to execute a non-secure process to produce non-secure data to be included in an output data stream, and to execute a secure process to produce secure data to be included in the output data stream. A non-secure buffer is provided for receiving the non-secure data produced by the non-secure process, and in addition a secure buffer is provided for receiving the secure data produced by the secure process, the secure buffer not being accessible by the non-secure process. An output controller is then arranged to read the non-secure data from the non-secure buffer and the secure data from the secure buffer, and to merge the non-secure data and the secure data in order to produce a combined data stream, the output data stream then being derivable from the combined data stream. It has been found that such an approach assists in improving the security of the secure data, and in reducing memory bandwidth requirements and the processing requirements of the processor.
摘要翻译： 本发明提供一种用于合并安全和非安全数据的数据处理装置和方法。 该装置包括至少一个处理器，可操作以执行非安全过程以产生要包括在输出数据流中的非安全数据，以及执行安全处理以产生要包括在输出数据流中的安全数据。 提供了一种非安全缓冲器，用于接收由非安全过程产生的非安全数据，另外还提供了一个安全缓冲器，用于接收由安全过程生成的安全数据，安全缓冲区不能被非安全性访问， 安全程序。 然后，输出控制器被安排为从非安全缓冲器读取非安全数据和来自安全缓冲器的安全数据，并且合并非安全数据和安全数据以产生组合数据流， 输出数据流然后可从组合数据流导出。 已经发现，这种方法有助于提高安全数据的安全性，并且在减少存储器带宽要求和处理器的处理要求方面有所帮助。
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