公开(公告)号：US07064999B2

公开(公告)日：2006-06-20

申请号：US10342901

申请日：2003-01-15

申请人： Helmut Fischer ,  Ullrich Menczigar ,  Johann Pfeiffer

发明人： Helmut Fischer ,  Ullrich Menczigar ,  Johann Pfeiffer

IPC分类号： G11C8/00

CPC分类号： G11C7/1042 ,  G11C7/1048 ,  G11C2207/002

摘要： A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

摘要翻译： 数字存储电路具有至少两对相邻的存储体。 每个存储体具有n个用于n个读/写数据线的并行端子。 每个银行对只有两束n / 2个读/写数据线。 第一束被分配给第一组的前半部分和第二组的第二半部分，并且第二组分配给第一组的后半部分和第二组的第二半部分。 数据与时钟信号的连续半周期的定时与n / 2输入/输出线并联输入/输出。 根据是否将数据分配给第一或第二半部分，可以在不同的切换状态之间改变用于将一束n / 2个输入/输出线连接到包含寻址的存储体的存储体对的读/写数据线的不同切换状态 时钟信号的周期。

公开(公告)号：US06903620B2

公开(公告)日：2005-06-07

申请号：US10452477

申请日：2003-06-02

申请人： Ullrich Menczigar ,  Helmut Fischer

发明人： Ullrich Menczigar ,  Helmut Fischer

IPC分类号： H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H03H7/38

CPC分类号： H01L23/5223 ,  H01L23/5228 ,  H01L23/647 ,  H01L27/0676 ,  H01L2223/6655 ,  H01L2924/0002 ,  H01L2924/19015 ,  H01L2924/00

摘要： An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

摘要翻译： RC网络集成在半导体电路芯片中，并连接在输入焊盘或引脚与耦合到芯片的基板的接地节点之间。 RC网络具有多个电阻元件，多个电容元件和多个连接/隔离元件，它们分别设置在至少一个电阻元件和各个电容元件之间。 根据连接/隔离元件的连接/隔离状态，本发明的电路配置能够实现输入电容和半导体电路芯片的输入电阻的可选和独立设置。

公开(公告)号：US06859411B2

公开(公告)日：2005-02-22

申请号：US10623831

申请日：2003-07-21

申请人： Johann Pfeiffer ,  Helmut Fischer

发明人： Johann Pfeiffer ,  Helmut Fischer

IPC分类号： G11C11/408 ,  G11C11/4097 ,  G11C8/00

CPC分类号： G11C11/4097 ,  G11C11/4087

摘要： A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

摘要翻译： 在动态存储器电路上执行用于写入和读取数据的方法。 存储器电路具有可通过字线和位线寻址的存储单元。 在使用特定地址寻址存储区域的情况下，字线被激活。 字线具有多个相互分离的字线部分。 通过位线，在与特定地址进行寻址的情况下，并行地将第一数量的数据写入由地址寻址的存储器单元，或者可以从地址寻址的存储单元读取第一数据数。 在使用特定地址进行寻址的情况下，只有一部分字线部分被激活，以便仅连接到字线的存储器单元的一部分被并行地并行地并行地读取。

公开(公告)号：US06711085B2

公开(公告)日：2004-03-23

申请号：US10266190

申请日：2002-10-07

申请人： Helmut Fischer ,  Johann Pfeiffer

发明人： Helmut Fischer ,  Johann Pfeiffer

IPC分类号： G11C800

CPC分类号： G11C11/4097 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4094

摘要： A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is subdivided into a plurality of adjacent groups which each form a segment. For each segment, provision is made of a separate set of two-conductor local data lines which lead via line switches to two-conductor master data lines common to all the memory areas. Furthermore, precharge devices are provided in order to equalize the potentials of the conductors of the local data lines and the conductors of the master data lines, the equalization potential for the local data lines being different than the equalization potential for the master data lines. A line switch control device provides for closing only of the line switches on those local data lines which belong to the segment in which a write or read mode takes place.

摘要翻译： 数字存储器电路包括多个区域，每个区域具有以行和列的矩阵形式设置的存储单元。 每个存储器区域的列被细分成多个相邻的组，每个组形成一个段。 对于每个段，提供一组单独的双导体本地数据线，其通过线路开关导通到所有存储区域共有的双导线主数据线。 此外，提供预充电装置以便均衡本地数据线的导体和主数据线的导体的电位，本地数据线的均衡电位与主数据线的均衡电位不同。 线路开关控制装置提供仅关闭属于发生写入或读取模式的段的那些本地数据线上的线路交换机。

公开(公告)号：US07428671B2

公开(公告)日：2008-09-23

申请号：US10452482

申请日：2003-06-02

申请人： Johann Pfeiffer ,  Helmut Fischer

发明人： Johann Pfeiffer ,  Helmut Fischer

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/26 ,  G11C11/401 ,  G11C2029/1206

摘要： A memory module has a memory cell configuration. For the purpose of testing the memory cell configuration, the memory module has a test structure with at least two test circuits, which are disposed in a distributed fashion on the memory module and are connected to one another via a common test switching bus, which can be connected to an address bus of the memory module via a decoupling circuit during a test operation.

摘要翻译： 存储器模块具有存储单元配置。 为了测试存储器单元配置，存储器模块具有测试结构，其具有至少两个测试电路，它们以分布的方式设置在存储器模块上，并且通过公共测试开关总线彼此连接，这可以 在测试操作期间通过去耦电路连接到存储器模块的地址总线。

公开(公告)号：US06928024B2

公开(公告)日：2005-08-09

申请号：US10639379

申请日：2003-08-12

申请人： Johann Pfeiffer ,  Helmut Fischer

发明人： Johann Pfeiffer ,  Helmut Fischer

IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/002

摘要： A RAM memory circuit has at least one memory bank with a multiplicity of memory cells arranged like a matrix in rows and columns and is subdivided into q≧2 areas, each of which comprises p≧1 segments each comprising a plurality of columns. Each segment is assigned a bundle of master data lines, which branches from an area bus assigned to the relevant area and, for its part, branches via a switching network to the memory cells of the relevant segment. The area buses can be connected cyclically to a common data port. In order to allow a read operation the beginning of which overlaps the end of a preceding write operation, each master data line bundle has coupled to it a data latch for holding the data respectively appearing there, and an isolating switch is in each case provided between each master data line bundle and the assigned area bus.

摘要翻译： RAM存储器电路具有至少一个存储体，存储单元排列成行和列中的矩阵，并被细分为q≥2个区域，每个区域包括每个包括多个列的p≥1个区段。 每个段被分配一束主数据线，其从分配给相关区域的区域总线分支，并且其一部分通过交换网络分支到相关段的存储器单元。 区域总线可以循环连接到公共数据端口。 为了允许其开始与先前写入操作的结束重叠的读取操作，每个主数据线束已经耦合到其上用于保持分别出现在那里的数据的数据锁存器，并且隔离开关分别位于 每个主数据线束和分配区总线。

公开(公告)号：US06711072B2

公开(公告)日：2004-03-23

申请号：US10266355

申请日：2002-10-07

申请人： Helmut Fischer ,  Johann Pfeiffer

发明人： Helmut Fischer ,  Johann Pfeiffer

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/4094 ,  G11C11/4097

摘要： A memory circuit contains areas having memory cells. To transfer memory data from/to the memory cells, two-wire local data lines are provided. Each of the local data lines is associated with one of the memory areas and is connected to a two-wire master data line, common to all the memory areas, by a line circuit-breaker. To represent the binary value of data on a local data line, the wires are driven, to first and second logic potentials. Each line circuit-breaker contains switching devices which, if one of the two wires in the local data line is at the second logic potential, autonomously transfer the potential to the associated wire in the master data line, and, if one of the two wires in the master data line is at the second logic potential, autonomously transfer the potential to the associated wire in the local data line.

摘要翻译： 存储器电路包含具有存储单元的区域。 为了将存储器数据从存储单元传送到存储单元，提供了两线本地数据线。 每个本地数据线与一个存储区域相关联，并通过线路断路器连接到所有存储器区域共用的两线主数据线。 为了表示本地数据线上的数据的二进制值，导线被驱动到第一和第二逻辑电位。 每个线路断路器包含开关装置，如果本地数据线中的两条导线之一处于第二逻辑电位，则将电位自主地转移到主数据线中的相关线，并且如果两条线之一 在主数据线处于第二逻辑电位时，自动将电位转移到本地数据线中的相关线。

公开(公告)号：US07278072B2

公开(公告)日：2007-10-02

申请号：US10429579

申请日：2003-05-05

申请人： Johann Pfeiffer ,  Helmut Fischer

发明人： Johann Pfeiffer ,  Helmut Fischer

IPC分类号： G11C29/26 ,  G11C29/50

CPC分类号： G11C29/12 ,  G11C11/401 ,  G11C29/40 ,  G11C2029/0405

摘要： The testing of a RAM memory circuit containing a multiplicity of memory cells can in each case be selected in groups of n≧1 memory cells by using an applied address information item in order to write in or read out groups of in each case n data. According to the invention, in a test write cycle, a plurality i=j*m of the memory cell groups are selected, where j and m are in each case integers ≧2, and the same datum is written into all the memory cells of in each case m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in a sequence such that the read-out data groups from in each case m memory cell groups at which the same datum was written in are provided simultaneously or in direct succession as a read data block comprising m*n data. Each time a read data block is provided, a compressed test result is determined and provided; the result indicates if all m*n data of the read data block provided correspond to the datum written therein.

摘要翻译： 在每种情况下，通过使用应用的地址信息项来选择包含多个存储器单元的RAM存储器电路的测试，以便在n个= 1个存储器单元的组中写入或读出在每种情况下的n个数据组 。 根据本发明，在测试写入周期中，选择存储单元组的多个i = j * m，其中j和m在每种情况下都是> = 2，并且相同的数据被写入所有存储单元 在每种情况下m个选择的存储单元组。 在随后的读取周期中，以写入周期中选择的i个存储器单元组被选择并读取，使得从每个情况读出数据组m个记录相同数据的存储单元组同时被提供 或作为包含m * n个数据的读取数据块的直接连续。 每次读取数据块时，都会确定并提供压缩测试结果; 结果指示所提供的读取数据块的所有m * n数据是否对应于其中写入的数据。

公开(公告)号：US06738309B2

公开(公告)日：2004-05-18

申请号：US10154597

申请日：2002-05-23

申请人： Alexander Benedix ,  Kazimierz Szczypinski ,  Helmut Fischer ,  Johann Pfeiffer

发明人： Alexander Benedix ,  Kazimierz Szczypinski ,  Helmut Fischer ,  Johann Pfeiffer

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

摘要： A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.

摘要翻译： 描述了具有时钟输入，信号输入，数据输出，测量装置，控制电路和等待时间的半导体存储器。 在信号输入的激活和在数据输出端要读取的数据的可用性之间经过了延迟。 时钟信号被馈送到时钟输入。 基于时钟信号，测量装置确定延迟的值，并且控制电路以半导体存储器的操作的确定值配置半导体存储器。

公开(公告)号：US06986088B2

公开(公告)日：2006-01-10

申请号：US10245622

申请日：2002-09-17

申请人： Helmut Fischer ,  Johann Pfeiffer ,  Rainer Florian Schnabel

发明人： Helmut Fischer ,  Johann Pfeiffer ,  Rainer Florian Schnabel

IPC分类号： G01R31/28

CPC分类号： G11C29/12005 ,  G11C29/12

摘要： The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.