公开(公告)号：US07064999B2

公开(公告)日：2006-06-20

申请号：US10342901

申请日：2003-01-15

申请人： Helmut Fischer ,  Ullrich Menczigar ,  Johann Pfeiffer

发明人： Helmut Fischer ,  Ullrich Menczigar ,  Johann Pfeiffer

IPC分类号： G11C8/00

CPC分类号： G11C7/1042 ,  G11C7/1048 ,  G11C2207/002

摘要： A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

摘要翻译： 数字存储电路具有至少两对相邻的存储体。 每个存储体具有n个用于n个读/写数据线的并行端子。 每个银行对只有两束n / 2个读/写数据线。 第一束被分配给第一组的前半部分和第二组的第二半部分，并且第二组分配给第一组的后半部分和第二组的第二半部分。 数据与时钟信号的连续半周期的定时与n / 2输入/输出线并联输入/输出。 根据是否将数据分配给第一或第二半部分，可以在不同的切换状态之间改变用于将一束n / 2个输入/输出线连接到包含寻址的存储体的存储体对的读/写数据线的不同切换状态 时钟信号的周期。

公开(公告)号：US06903620B2

公开(公告)日：2005-06-07

申请号：US10452477

申请日：2003-06-02

申请人： Ullrich Menczigar ,  Helmut Fischer

发明人： Ullrich Menczigar ,  Helmut Fischer

IPC分类号： H01L23/522 ,  H01L23/64 ,  H01L27/06 ,  H03H7/38

CPC分类号： H01L23/5223 ,  H01L23/5228 ,  H01L23/647 ,  H01L27/0676 ,  H01L2223/6655 ,  H01L2924/0002 ,  H01L2924/19015 ,  H01L2924/00

摘要： An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

摘要翻译： RC网络集成在半导体电路芯片中，并连接在输入焊盘或引脚与耦合到芯片的基板的接地节点之间。 RC网络具有多个电阻元件，多个电容元件和多个连接/隔离元件，它们分别设置在至少一个电阻元件和各个电容元件之间。 根据连接/隔离元件的连接/隔离状态，本发明的电路配置能够实现输入电容和半导体电路芯片的输入电阻的可选和独立设置。

公开(公告)号：US09605940B2

公开(公告)日：2017-03-28

申请号：US14119953

申请日：2012-05-24

申请人： Helmut Fischer

发明人： Helmut Fischer

IPC分类号： G01B7/06

CPC分类号： G01B7/10 ,  G01B7/105 ,  Y10T29/49071

摘要： The invention relates to a measuring probe for measuring the thickness of thin layers with a housing, having at least one sensor element, which is received in the housing at least slightly moveably along a longitudinal axis and which comprises at least one winding device, which is allocated to the longitudinal axis, having a spherical positioning cap facing the outer front face of the housing, said cap being arranged in the longitudinal axis, wherein the spherical positioning cap has a basic body that has a cylindrical core section and a pole cap arranged on a front face of the core section, wherein the winding device is allocated to the spherical positioning cap, said winding device being formed from a discoidal or annular carrier with at least one Archimedean coil arranged thereon and with the basic body consisting of a ferritic material and the pole cap consisting of a hard metal.

公开(公告)号：US07784325B2

公开(公告)日：2010-08-31

申请号：US11599600

申请日：2006-11-14

申请人： Helmut Fischer

发明人： Helmut Fischer

IPC分类号： G01B3/30

CPC分类号： G01B7/105

摘要： The invention relates to a calibration standard, especially for the calibration of devices for the non-destructive measurement of the thickness of thin layers with a carrier plate (16) of a basic material and a standard (17) applied on the carrier plate (16), said standard having the thickness of the layer at which the device is to be calibrated, wherein that a holding device (22) arranged on the basic body (12) of the calibration standard (11) receives at least the standard (17) to the basic body (12) such that upon setting a measuring probe of the device for the non-destructive measurement of thin layers onto the standard (17), its position will be changeable by at least one degree of freedom.

摘要翻译： 本发明涉及一种校准标准，特别是用于校准具有基材的载体板（16）和施加在载体板（16）上的标准物（17）的薄层厚度的非破坏性测量的装置 ），所述标准具有要在其上校准装置的层的厚度，其中布置在校准标准（11）的基体（12）上的保持装置（22）至少接收标准（17） 到基体（12），使得当将用于薄层的非破坏性测量的装置的测量探针设置到标准（17）上时，其位置将可以至少一个自由度改变。

公开(公告)号：US07359278B2

公开(公告)日：2008-04-15

申请号：US11009557

申请日：2004-12-10

申请人： Helmut Fischer

发明人： Helmut Fischer

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C11/4076

摘要： A method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of the memory module for carrying out operations in accordance with a predetermined specification of the memory module. The command decoding device is formed with a decision memory containing memory locations Mi,j, the storage capacity of which suffices to receive, for an arbitrary specification from a plurality of different specifications, a decision information item specifying whether or how the second operation command of selected pairs of two directly successive operation commands is to be executed. After integration of the command decoding device thus formed, the decision information items demanded in the case of the predetermined specification are written to the memory locations of the decision memory.

摘要翻译： 一种用于产生集成存储器模块的方法，所述集成存储器模块包含响应于外部操作命令的命令解码装置，以根据所述存储器模块的预定规格来设置用于执行操作的存储器模块的操作状态。 命令解码装置形成有判定存储器，该判定存储器包含存储器位置M i，j，其存储容量对于来自多个不同规格的任意规范就足以接收指定的决定信息项 是否要执行所选择的两个直接连续操作命令的对的第二操作命令。 在如此形成的命令解码装置的集成之后，将在预定规格的情况下所要求的判定信息项写入决定存储器的存储单元。

公开(公告)号：US07180286B2

公开(公告)日：2007-02-20

申请号：US10705107

申请日：2003-11-10

申请人： Helmut Fischer ,  Bernhard Scherzinger

发明人： Helmut Fischer ,  Bernhard Scherzinger

IPC分类号： G01B7/06

CPC分类号： G01B21/08

摘要： An apparatus for non-destructive measurement of the thickness of thin layers, has a housing and a probe which is connected to an evaluation unit and to which signals are emitted during a measurement for determining the layer thickness, and having a display apparatus which indicates at least the measurement data from the evaluation unit. At least one further display apparatus is positioned on the housing away from the plane of the first display apparatus.

摘要翻译： 用于非破坏性地测量薄层厚度的装置具有壳体和探头，其连接到评估单元并且在用于确定层厚度的测量期间发射信号，并且具有指示在 最少来自评估单元的测量数据。 至少一个另外的显示装置被定位在远离第一显示装置的平面的壳体上。

公开(公告)号：US20060076979A1

公开(公告)日：2006-04-13

申请号：US11244856

申请日：2005-10-06

申请人： Paul Brucke ,  Helmut Fischer

发明人： Paul Brucke ,  Helmut Fischer

IPC分类号： H03K19/0175

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C11/4093 ,  H03K19/00384 ,  H03K19/018521

摘要： A prestage for generating a control signal for an output driver of an integrated circuit, wherein the integrated circuit can be provided with a reference potential and a supply potential fixed in relation to the reference potential, comprises an input for receiving an input signal from the integrated circuit, a circuitry for generating an output signal based on the received input signal, an output for outputting the generated output signals as control signal for an output driver as well as a current source, which is effectively connected to the circuitry. Thereby, the circuitry for generating an output signal and the current source are connected in series and connected to a first potential and a second potential such that a prestage potential difference across the series circuit is higher than a supply potential difference between the supply potential and the reference potential. Such a prestage has the advantage that it is less sensitive against variations on the reference potential or the reference potential, respectively, than conventional circuitries and can generate an output signal with well defined rise times.

摘要翻译： 一种用于产生用于集成电路的输出驱动器的控制信号的前置放大器，其中所述集成电路可以被提供有相对于所述参考电位固定的参考电位和电源电位，包括用于接收来自所述集成电路的输入信号的输入 电路，用于基于接收的输入信号产生输出信号的电路，用于输出所生成的输出信号作为输出驱动器的控制信号的输出以及有效地连接到电路的电流源。 因此，用于产生输出信号和电流源的电路串联连接并连接到第一电位和第二电位，使得串联电路两端的前置电位差高于电源电压和 参考潜力。 这样的前置放大器的优点在于，它比传统电路分别对参考电位或参考电位的变化较不敏感，并且可以产生具有明确定义的上升时间的输出信号。

公开(公告)号：US20050270101A1

公开(公告)日：2005-12-08

申请号：US11128625

申请日：2005-05-13

申请人： Rory Dickman ,  Helmut Fischer

发明人： Rory Dickman ,  Helmut Fischer

IPC分类号： H03F1/30 ,  H03F3/45

CPC分类号： H03F1/301 ,  H03F3/45183

摘要： The present invention relates to an input circuit for receiving an input signal in an integrated circuit, having a differential amplifier whose first input can have a predetermined reference voltage applied to it and whose second input can have the input signal applied to it, and having a current source for operating the differential amplifier at its operating point, wherein a setting circuit is connected to the current source in order to set the operating point of the differential amplifier in an optimum manner on the basis of the predetermined reference voltage.

摘要翻译： 本发明涉及一种用于在集成电路中接收输入信号的输入电路，其具有差分放大器，该差分放大器的第一输入可以具有施加到其上的预定参考电压，并且其第二输入可以具有施加到其上的输入信号，并且具有 用于在其工作点操作差分放大器的电流源，其中设置电路连接到电流源，以便基于预定参考电压以最佳方式设置差分放大器的工作点。

公开(公告)号：US06920074B2

公开(公告)日：2005-07-19

申请号：US10642906

申请日：2003-08-18

申请人： Helmut Fischer ,  Kazimierz Szczypinski

发明人： Helmut Fischer ,  Kazimierz Szczypinski

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/06

摘要： In a semiconductor memory, there is capacitive coupling between bit lines that largely run in parallel. Outer sections of the bit lines are connected via respective switches to a sense amplifier arranged between the switches. When a memory cell is being read, the capacitive interference by other bit lines that are not coupled to the memory cell being read is kept as low as possible before the start of amplification by the sense amplifier by turning on the switches in that bit line. During the amplification phase, the remote outer section of that bit line is disconnected using the appropriate switch. In one embodiment, the capacitance of the bit line that is not connected to the memory cell to be read is increased further by additionally activating a precharging circuit.

摘要翻译： 在半导体存储器中，存在大量平行运行的位线之间的电容耦合。 位线的外部部分经由相应的开关连接到布置在开关之间的读出放大器。 当正在读取存储器单元时，通过接通该位线中的开关，由读出放大器开始放大之前，未耦合到正在读取的存储器单元的其它位线的电容性干扰保持尽可能低。 在放大阶段期间，使用适当的开关断开该位线的远程外部部分。 在一个实施例中，通过附加地激活预充电电路来进一步增加未连接到要读取的存储器单元的位线的电容。

公开(公告)号：US06759879B2

公开(公告)日：2004-07-06

申请号：US10429158

申请日：2003-05-02

申请人： Helmut Fischer ,  Kazimierz Szczypinski

发明人： Helmut Fischer ,  Kazimierz Szczypinski

IPC分类号： H03K1700

CPC分类号： G11C7/225 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2227

摘要： A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, as well as a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit. In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off. A reduced current consumption can be achieved by the present invention in this way.

摘要翻译： 存储电路包括：第一时钟接收器电路，用于接收外部时钟信号，以便从所述外部时钟信号产生第一内部时钟信号，并输出第一内部时钟信号以在存储电路内使用，以及 第二时钟接收器电路，用于接收所述外部时钟信号，并且用于从所述外部时钟信号产生第二内部时钟信号，所述第二时钟接收器电路比所述第一时钟接收器电路消耗更少的电流。 此外，提供了一个电路块，其基于所述第一或第二内部时钟信号进行操作，并且当存在掉电预充电模式时用于关断所述第一时钟接收器电路，所述电路块在 当所述第一时钟接收器电路已被切断时，所述第二内部时钟信号的基础。 通过本发明可以以这种方式实现减少的电流消耗。