利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.028 秒)

    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME
    1.
    发明申请
    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF FABRICATING SAME 有权
    金属绝缘子金属（MIM）电容器及其制造方法

    公开(公告)号：US20070063244A1

    公开(公告)日：2007-03-22

    申请号：US11162776

    申请日：2005-09-22

    申请人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    发明人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203

    摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

    摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）的半导体器件。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME
    2.
    发明申请
    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME 失效
    与中间金属接触集成的金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US20070218625A1

    公开(公告)日：2007-09-20

    申请号：US11750355

    申请日：2007-05-18

    申请人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    发明人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material. The semiconductor device contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region.

    摘要翻译： 本发明涉及一种制造工艺的方法，该方法将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。 半导体器件包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选地至少一个场效应晶体管（FET）。 沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。

    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME
    3.
    发明申请
    TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME 有权
    与中间金属接触集成的金属绝缘体金属（MIM）电容器及其制造方法

    公开(公告)号：US20070057302A1

    公开(公告)日：2007-03-15

    申请号：US11162413

    申请日：2005-09-09

    申请人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    发明人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

    IPC分类号： H01L29/94 ,  H01L21/20

    CPC分类号： H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region. The present invention also relates to a fabrication process, which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material.

    摘要翻译： 本发明涉及一种半导体器件，其包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选至少一个场效应晶体管（FET）。 沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。 本发明还涉及一种制造工艺，其将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。

    VERTICAL SOI TRENCH SONOS CELL
    6.
    发明申请
    VERTICAL SOI TRENCH SONOS CELL 有权
    垂直SOI TRENCH SONOS电池

    公开(公告)号：US20070122971A1

    公开(公告)日：2007-05-31

    申请号：US11164513

    申请日：2005-11-28

    申请人： David Dobuzinsky ,  Herbert Ho ,  Jack Mandelman ,  Yoichi Otani

    发明人： David Dobuzinsky ,  Herbert Ho ,  Jack Mandelman ,  Yoichi Otani

    IPC分类号： H01L21/336 ,  H01L27/12

    CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

    摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

    摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

    Ferromagnetic memory cell and methods of making and using the same
    7.
    发明申请
    Ferromagnetic memory cell and methods of making and using the same 有权
    铁磁记忆单元及其制造和使用方法

    公开(公告)号：US20070045686A1

    公开(公告)日：2007-03-01

    申请号：US11216387

    申请日：2005-08-31

    申请人： Kangguo Cheng ,  Herbert Ho ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Herbert Ho ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L29/94

    CPC分类号： G11C11/15 ,  H01L27/1203 ,  H01L43/065

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。 铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。 提供了许多其他方面。

    STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
    8.
    发明申请
    STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY, TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS 有权
    用于SOC应用的高密度，基于TRENCH的非易失性随机接入SONOS存储器细胞的构造和方法

    公开(公告)号：US20060226474A1

    公开(公告)日：2006-10-12

    申请号：US10907686

    申请日：2005-04-12

    申请人： Herbert Ho ,  Jack Mandelman ,  Tak Ning ,  Yoichi Otani

    发明人： Herbert Ho ,  Jack Mandelman ,  Tak Ning ,  Yoichi Otani

    IPC分类号： H01L29/792

    CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

    摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located within a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

    摘要翻译： 本发明提供具有随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。 在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于沟槽深度为1至2μm的沟槽结构内，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。