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    Method of fabricating a semiconductor memory device
    4.
    发明授权
    Method of fabricating a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5248628A

    公开(公告)日：1993-09-28

    申请号：US896537

    申请日：1992-06-09

    申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

    发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

    摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。

    Method of manufacturing a semiconductor device and semiconductor device manufactured according to the method
    5.
    发明授权
    Method of manufacturing a semiconductor device and semiconductor device manufactured according to the method 失效
    根据该方法制造的半导体器件和半导体器件的制造方法

    公开(公告)号：US5923073A

    公开(公告)日：1999-07-13

    申请号：US932388

    申请日：1997-09-17

    申请人： Masami Aoki ,  Hiroshi Takato

    发明人： Masami Aoki ,  Hiroshi Takato

    IPC分类号： H01L21/20 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/76 ,  H01L29/78 ,  H01L29/72

    CPC分类号： H01L21/76 ,  Y10S148/015

    摘要： A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer.The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.

    摘要翻译： 由沟槽部分隔离的半导体器件和半导体器件的制造方法。 沟槽部分用Si外延生长层再填充。 沟槽在其侧壁上具有第一绝缘层，并且在沟槽的顶部上以自对准方式氧化形成第二绝缘层作为覆盖层。 形成在衬底上的半导体器件被沟槽隔离。 由衬底和Si外延层之间的应力产生的过度的漏电流减小。 通过盖层抑制沟槽角部处的场效应的集中。 再填充步骤也可以同时且均匀地制成具有较宽开口的沟槽和具有较窄开口的另一个沟槽。

    MOS-type semiconductor integrated circuit device
    6.
    发明授权
    MOS-type semiconductor integrated circuit device 失效
    MOS型半导体集成电路器件

    公开(公告)号：US5258635A

    公开(公告)日：1993-11-02

    申请号：US754191

    申请日：1991-08-28

    申请人： Akihiro Nitayama ,  Hiroshi Takato ,  Fumio Horiguchi ,  Fujio Masuoka

    发明人： Akihiro Nitayama ,  Hiroshi Takato ,  Fumio Horiguchi ,  Fujio Masuoka

    IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/26

    CPC分类号： H01L27/0928 ,  H01L27/1104 ,  H01L29/7827 ,  Y10S257/904

    摘要： A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.

    摘要翻译： 提供了一种MOS型半导体集成电路器件，其中MOS晶体管形成为垂直配置。 MOS晶体管由形成在基板上的柱层构成。 柱层的外周面用于形成MOS晶体管的栅极。 因此，可以在小的区域内获得其大的栅极宽度。 结果，可以在保持规定的载流能力的同时显着地减小MOS晶体管的总芯片面积。

    Method of fabricating a trench capacitor
    8.
    发明授权
    Method of fabricating a trench capacitor 有权
    制造沟槽电容器的方法

    公开(公告)号：US06312982B1

    公开(公告)日：2001-11-06

    申请号：US09351182

    申请日：1999-07-12

    申请人： Hiroshi Takato ,  Koichi Kokubun

    发明人： Hiroshi Takato ,  Koichi Kokubun

    IPC分类号： H01L218242

    CPC分类号： H01L27/10888 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10894

    摘要： This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the same. A memory cell is constructed of capacitors formed in two end portions of an element formation region of a silicon substrate and a MOS transistor formed between these capacitors. The interval between gate electrodes of MOS transistors in adjacent memory cells is made larger than the intervals between these gate electrodes and gate electrodes formed outside the former gate electrodes. A portion above an n-type diffusion layer connected to a capacitor node is filled with a spacer insulating film, and an n-type diffusion layer connected to a bit line is covered with the spacer insulating film. A titanium silicide film is formed on one of these n-type diffusion layers and the gate electrodes. In a first transistor in a memory cell array, a metal silicide film is not formed on the surfaces of source and drain diffusion layers and is formed only on the surface of a gate electrode. In a second transistor in a logic circuit, a metal silicide film is formed on the surfaces of source and drain diffusion layers and a gate electrode.

    摘要翻译： 本发明提供一种可以在不增加制造步骤的数量的情况下获得高速DRAM单元和逻辑电路的半导体器件及其制造方法。 存储单元由形成在硅衬底的元件形成区域的两个端部中的电容器和形成在这些电容器之间的MOS晶体管构成。 使相邻存储单元中的MOS晶体管的栅电极之间的间隔大于形成在前栅电极外的这些栅电极与栅电极之间的间隔。 连接到电容器节点的n型扩散层上方的部分填充有间隔绝缘膜，并且与间位绝缘膜覆盖连接到位线的n型扩散层。 在这些n型扩散层和栅电极之一上形成硅化钛膜。 在存储单元阵列中的第一晶体管中，在源极和漏极扩散层的表面上不形成金属硅化物膜，并且仅形成在栅电极的表面上。 在逻辑电路中的第二晶体管中，在源极和漏极扩散层和栅电极的表面上形成金属硅化物膜。

    Method of manufacturing a semiconductor device isolated by a trench
    9.
    发明授权
    Method of manufacturing a semiconductor device isolated by a trench 失效
    制造由沟槽隔离的半导体器件的方法

    公开(公告)号：US5384280A

    公开(公告)日：1995-01-24

    申请号：US906654

    申请日：1992-06-30

    申请人： Masami Aoki ,  Hiroshi Takato

    发明人： Masami Aoki ,  Hiroshi Takato

    IPC分类号： H01L21/20 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/318 ,  H01L21/336 ,  H01L21/76 ,  H01L29/78 ,  H01L21/308

    CPC分类号： H01L21/76 ,  Y10S148/015

    摘要： A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer. The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.

    摘要翻译： 由沟槽部分隔离的半导体器件和半导体器件的制造方法。 沟槽部分用Si外延生长层再填充。 沟槽在其侧壁上具有第一绝缘层，并且在沟槽的顶部上以自对准方式氧化形成第二绝缘层作为覆盖层。 形成在衬底上的半导体器件被沟槽隔离。 由衬底和Si外延层之间的应力产生的过度的漏电流减小。 通过盖层抑制沟槽角部处的场效应的集中。 再填充步骤也可以同时且均匀地制成具有较宽开口的沟槽和具有较窄开口的另一个沟槽。

    Semiconductor memory device and its fabricating method
    10.
    发明授权
    Semiconductor memory device and its fabricating method 失效
    半导体存储器件及其制造方法

    公开(公告)号：US5144579A

    公开(公告)日：1992-09-01

    申请号：US578608

    申请日：1990-09-07

    申请人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

    发明人： Naoko Okabe ,  Satoshi Inoue ,  Kazumasa Sunouchi ,  Takashi Yamada ,  Akihiro Nitayama ,  Hiroshi Takato

    IPC分类号： H01L27/04 ,  H01L21/28 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10808

    摘要： A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

    摘要翻译： 一种半导体存储器件，其中存储节点接触孔和位线接触孔中的至少一个包括在形成在栅电极上的第一层间绝缘膜中形成的第一接触孔和在第二互连孔中形成的第二接触孔， 在导电材料上形成的层间绝缘膜，该导电材料在与导电材料接触的第一接触孔中嵌入高于栅电极的电平，通过蚀刻第二层间绝缘膜的一部分而露出导电材料 从而可以使存储器件的尺寸小并且可以提高可靠性。 此外，在高于位线的层中形成电容器，从而不需要对单元阵列内的平板电极进行图案化，便于存储节点电极的处理以增加电容器面积并提高可靠性。 利用上述结构，去除了嵌入层之间的短路，形成了第二层间绝缘膜的良好质量。