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公开(公告)号：US20240098898A1
公开(公告)日：2024-03-21
申请号：US17949732
申请日：2022-09-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Melvin Kent Benedict , Chi Kim Sides , Paul Danna , Michael Chan
CPC classification number: H05K1/115 , H05K3/4038 , H05K2201/09545 , H05K2203/0207
Abstract: One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.
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公开(公告)号：US20230292436A1
公开(公告)日：2023-09-14
申请号：US17689611
申请日：2022-03-08
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Melvin K. Benedict , Paul Danna , Chi Kim Sides , Wayne Vuong , Michael Chan
CPC classification number: H05K1/115 , H05K1/0298 , H05K2201/09263 , H05K2201/09609
Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.
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Patent Agency Ranking
公开(公告)号：US12068554B2
公开(公告)日：2024-08-20
申请号：US17587818
申请日：2022-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Paul Danna , Vincent W. Michna , Chi Kim Sides
CPC classification number: H01R12/716 , H01R12/707 , H01R43/0256 , H05K3/3405
Abstract: A dual-path signal interconnect is provided. The interconnect can include a first signal trace, first and second solder pads positioned above and connected to the first signal trace, and a third solder pad. The second solder pad separates from the first solder pad. The third solder pad separates from the second solder pad and is connected to a second signal trace. The first and second solder pads are to allow a pin of a connector to be soldered to the first and second solder pads, such that, when the pin of the external connector is soldered, high-speed electrical signals from the first signal trace are routed to the connector. The second and third solder pads are to allow a conductor to be soldered to the second and third solder pads, such that, when the conductor is soldered, the high-speed electrical signals are routed to the second signal trace.
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公开(公告)号：US20230246353A1
公开(公告)日：2023-08-03
申请号：US17587818
申请日：2022-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Paul Danna , Vincent W. Michna , Chi Kim Sides
CPC classification number: H01R12/716 , H01R12/707 , H01R43/0256 , H05K3/3405
Abstract: A dual-path signal interconnect is provided. The interconnect can include a first signal trace, first and second solder pads positioned above and connected to the first signal trace, and a third solder pad. The second solder pad separates from the first solder pad. The third solder pad separates from the second solder pad and is connected to a second signal trace. The first and second solder pads are to allow a pin of a connector to be soldered to the first and second solder pads, such that, when the pin of the external connector is soldered, high-speed electrical signals from the first signal trace are routed to the connector. The second and third solder pads are to allow a conductor to be soldered to the second and third solder pads, such that, when the conductor is soldered, the high-speed electrical signals are routed to the second signal trace.
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公开(公告)号：US11381017B2
公开(公告)日：2022-07-05
申请号：US16847924
申请日：2020-04-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Franz , Brian T. Purcell , Paul Danna
Abstract: A method and system are disclosed that allow easier coupling between high-density connectors. In one example implementation, the connectors on a computer board are mounted on flexible tabs extending from the computer board, the tabs having been formed by cutting slots on both sides of each of the tabs. A milled section within each tab makes the tab thinner, allowing it additional flexibility. In another example implementation, a pass-through connector is used as an intermediary between two mating connectors. The pass-through connector has internal pins with greater tolerance than the tolerance between the two mating connectors, allowing it easier alignment of pins for coupling. In yet another example implementation, mating connectors are coupled using a bundle of cables between the mating connectors that allows the coupling of multiple connectors, one at a time, reducing or eliminating the need to simultaneously couple multiple connectors.
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公开(公告)号：US11937373B2
公开(公告)日：2024-03-19
申请号：US17689611
申请日：2022-03-08
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Melvin K. Benedict , Paul Danna , Chi Kim Sides , Wayne Vuong , Michael Chan
CPC classification number: H05K1/115 , H05K1/0222 , H05K1/0245 , H05K1/0251 , H05K1/0298 , H05K1/116 , H05K2201/09263 , H05K2201/09609
Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.
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公开(公告)号：US20210320443A1
公开(公告)日：2021-10-14
申请号：US16847924
申请日：2020-04-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： John Franz , Brian T. Purcell , Paul Danna
Abstract: A method and system are disclosed that allow easier coupling between high-density connectors. In one example implementation, the connectors on a computer board are mounted on flexible tabs extending from the computer board, the tabs having been formed by cutting slots on both sides of each of the tabs. A milled section within each tab makes the tab thinner, allowing it additional flexibility. In another example implementation, a pass-through connector is used as an intermediary between two mating connectors. The pass-through connector has internal pins with greater tolerance than the tolerance between the two mating connectors, allowing it easier alignment of pins for coupling. In yet another example implementation, mating connectors are coupled using a bundle of cables between the mating connectors that allows the coupling of multiple connectors, one at a time, reducing or eliminating the need to simultaneously couple multiple connectors.
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