公开(公告)号：US06777736B2

公开(公告)日：2004-08-17

申请号：US09971737

申请日：2001-10-09

申请人： Kaoru Saigoh ,  Hisashi Miyazawa ,  Hirokazu Yamazaki ,  Hideaki Suzuki

发明人： Kaoru Saigoh ,  Hisashi Miyazawa ,  Hirokazu Yamazaki ,  Hideaki Suzuki

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509

摘要： The semiconductor device having the capacitor comprises a plurality of switching elements formed on a semiconductor substrate 1 at a distance, a plurality of capacitors formed in areas between a plurality of switching elements formed in the first direction respectively and each having a lower electrode, a dielectric film and an upper electrode, first wirings for connecting the upper electrodes of the capacitors and the switching elements in the first direction on a one-by-one base, and second wirings formed over a part of the first wirings, the switching elements, and the capacitors to extend in the second direction that intersects with the first direction. Accordingly, the higher speed operation than the prior art can be achieved.

摘要翻译： 具有电容器的半导体器件包括在半导体衬底1上形成一定距离的多个开关元件，多个电容器形成在分别形成在第一方向上的多个开关元件之间的区域中，并且各自具有下电极，电介质 薄膜和上电极，第一布线，用于在一个接一个的基底上连接电容器的上电极和第一方向的开关元件，以及形成在第一布线的一部分上的第二布线，开关元件和 电容器沿与第一方向相交的第二方向延伸。 因此，可以实现比现有技术更高的速度操作。

公开(公告)号：US06496428B2

公开(公告)日：2002-12-17

申请号：US09964642

申请日：2001-09-28

申请人： Chikai Ohno ,  Hirokazu Yamazaki ,  Hideaki Suzuki

发明人： Chikai Ohno ,  Hirokazu Yamazaki ,  Hideaki Suzuki

IPC分类号： G11C700

CPC分类号： G11C29/789 ,  G11C29/84 ,  G11C29/846

摘要： A redundancy information region having memory cells for retaining relief information indicating the locations of defective memory cells is arranged closer to at least one of a word driver or a plate driver than a memory cell region and a redundancy memory cell region. Since the memory cells of the redundancy information region start operation earlier, a relief/no-relief judgment can be made earlier, allowing reduction in access time. Besides, in memory cell operations, the defective memory cells are deselected in accordance with address information held in a redundancy address region. Redundancy memory cells for relieving the defective memory cells are selected in accordance with the relief information held in a redundancy flag region. Since the redundancy memory cells are selected without using the address information, it is possible to reduce the time that elapses before the redundancy memory cells are selected after the selection of word lines.

摘要翻译： 具有用于保存指示有缺陷存储单元的位置的释放信息的存储单元的冗余信息区被布置成比存储单元区域和冗余存储单元区域更靠近字驱动器或板驱动器中的至少一个。 由于冗余信息区域的存储单元早期开始操作，因此可以更早地进行缓解/不缓解判断，从而允许访问时间减少。 此外，在存储单元操作中，根据保存在冗余地址区域中的地址信息来取消选择不良存储单元。 根据保存在冗余标志区域中的补救信息来选择用于解除有缺陷的存储器单元的冗余存储单元。 由于在不使用地址信息的情况下选择冗余存储单元，所以可以在选择字线之后减少冗余存储单元之前经过的时间。

公开(公告)号：US07545186B2

公开(公告)日：2009-06-09

申请号：US10998060

申请日：2004-11-29

申请人： Hideaki Suzuki ,  Hirokazu Yamazaki

发明人： Hideaki Suzuki ,  Hirokazu Yamazaki

IPC分类号： H02H3/24

CPC分类号： H03K17/223 ,  H03K3/356008

摘要： A reset circuit includes a power supply detection circuit, a power-down detection circuit, and an output circuit. The power supply detection circuit outputs a first signal when a first voltage according to a power supply voltage is higher than a first threshold and outputting a second signal when the first voltage is lower than the first threshold during power-on and power-down. The power-down detection circuit outputs a third signal when a second voltage according to the power supply voltage becomes lower than a second threshold after the second signal is outputted during power-down. The output circuit outputs a power-on reset signal which changes from low to high when the first signal is outputted during power-on and outputs a power-down reset signal which changes from low to high when the third signal is outputted during power-down.

摘要翻译： 复位电路包括电源检测电路，掉电检测电路和输出电路。 当电源电压的第一电压高于第一阈值时，电源检测电路输出第一信号，并且在上电和掉电期间当第一电压低于第一阈值时输出第二信号。 当在掉电期间输出第二信号之后，当根据电源电压的第二电压变得低于第二阈值时，掉电检测电路输出第三信号。 输出电路在上电时输出第一个信号时，输出从低电平变为高电平的上电复位信号，并在断电时输出第三个信号输出时从低电平变为高电平的掉电复位信号 。

公开(公告)号：US20050275437A1

公开(公告)日：2005-12-15

申请号：US10998060

申请日：2004-11-29

申请人： Hideaki Suzuki ,  Hirokazu Yamazaki

发明人： Hideaki Suzuki ,  Hirokazu Yamazaki

IPC分类号： H03K3/356 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  H03K3/356008

摘要： A reset circuit includes a power supply detection circuit, a power-down detection circuit, and an output circuit. The power supply detection circuit outputs a first signal when a first voltage according to a power supply voltage is higher than a first threshold and outputting a second signal when the first voltage is lower than the first threshold during power-on and power-down. The power-down detection circuit outputs a third signal when a second voltage according to the power supply voltage becomes lower than a second threshold after the second signal is outputted during power-down. The output circuit outputs a power-on reset signal which changes from low to high when the first signal is outputted during power-on and outputs a power-down reset signal which changes from low to high when the third signal is outputted during power-down.

摘要翻译： 复位电路包括电源检测电路，掉电检测电路和输出电路。 当电源电压的第一电压高于第一阈值时，电源检测电路输出第一信号，并且在上电和掉电期间当第一电压低于第一阈值时输出第二信号。 当在掉电期间输出第二信号之后，当根据电源电压的第二电压变得低于第二阈值时，掉电检测电路输出第三信号。 输出电路在上电时输出第一个信号时，输出从低电平变为高电平的上电复位信号，并在断电时输出第三个信号输出时从低电平变为高电平的掉电复位信号 。

公开(公告)号：US08542041B2

公开(公告)日：2013-09-24

申请号：US12755119

申请日：2010-04-06

申请人： Mitsuhiro Ogai ,  Hirokazu Yamazaki ,  Keizo Morita ,  Kazuaki Yamane ,  Yasuhiro Fujii ,  Kazuaki Takai ,  Shoichiro Kawashima

发明人： Mitsuhiro Ogai ,  Hirokazu Yamazaki ,  Keizo Morita ,  Kazuaki Yamane ,  Yasuhiro Fujii ,  Kazuaki Takai ,  Shoichiro Kawashima

IPC分类号： H03L7/00

CPC分类号： G11C5/147

摘要： A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.

摘要翻译： 第一晶体管具有耦合到第一电源线和耦合到第一节点的另一端的一端和栅极。 第二晶体管具有耦合到第二节点的栅极，耦合到第一节点的一端和耦合到第三节点的另一端。 第三晶体管具有耦合到第二电源线的一端，耦合到第四节点的栅极和耦合到第三节点的另一端。 第一偏置电压产生电路向第二节点提供第一偏置电压。 第二偏置电压产生电路向第四节点提供第二偏置电压。 因此，第三节点从一定电平变化到另一电平的电源电压被设定为高电平，并且当电源电压降低时半导体器件中的内部节点被可靠地初始化。

公开(公告)号：US5402380A

公开(公告)日：1995-03-28

申请号：US192821

申请日：1994-02-07

申请人： Sinsuke Kumakura ,  Hirokazu Yamazaki ,  Hisayoshi Watanabe ,  Yasushi Kasa

发明人： Sinsuke Kumakura ,  Hirokazu Yamazaki ,  Hisayoshi Watanabe ,  Yasushi Kasa

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C7/06 ,  G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/02

CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C2029/5006

摘要： An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory including word lines WLi and bit lines BLi, a memory cell matrix 17 including nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

摘要翻译： 本发明的目的是提供一种能够容易且有效地进行测试的半导体器件。 包括字线WLi和位线BLi的非易失性半导体存储器，包括非易失性存储单元Cij的存储单元矩阵17，读出放大器15，用于执行写入和擦除操作所需的定时控制的写入/擦除定时电路9以及状态 寄存器2，用于在电路9的操作完成时存储存储器的工作状态，其中在存储单元矩阵17的地址之外提供两种虚拟单元D1，D2，D3。 。 。 ，其值固定为从感测放大器15引起不同输出的不同值。通过访问虚拟单元来产生通过条件或失败条件。

公开(公告)号：US20100253419A1

公开(公告)日：2010-10-07

申请号：US12755119

申请日：2010-04-06

申请人： Mitsuhiro OGAI ,  Hirokazu Yamazaki ,  Keizo Morita ,  Kazuaki Yamane ,  Yasuhiro Fujii ,  Kazuaki Takai ,  Shoichiro Kawashima

发明人： Mitsuhiro OGAI ,  Hirokazu Yamazaki ,  Keizo Morita ,  Kazuaki Yamane ,  Yasuhiro Fujii ,  Kazuaki Takai ,  Shoichiro Kawashima

IPC分类号： G05F3/02

CPC分类号： G11C5/147

摘要： A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.

摘要翻译： 第一晶体管具有耦合到第一电源线和耦合到第一节点的另一端的一端和栅极。 第二晶体管具有耦合到第二节点的栅极，耦合到第一节点的一端和耦合到第三节点的另一端。 第三晶体管具有耦合到第二电源线的一端，耦合到第四节点的栅极和耦合到第三节点的另一端。 第一偏置电压产生电路向第二节点提供第一偏置电压。 第二偏置电压产生电路向第四节点提供第二偏置电压。 因此，第三节点从一定电平变化到另一电平的电源电压被设定为高电平，并且当电源电压降低时半导体器件中的内部节点被可靠地初始化。

公开(公告)号：US5566386A

公开(公告)日：1996-10-15

申请号：US471526

申请日：1995-06-06

申请人： Sinsuke Kumakura ,  Hirokazu Yamazaki ,  Hisayoshi Watanabe ,  Yasushi Kasa

发明人： Sinsuke Kumakura ,  Hirokazu Yamazaki ,  Hisayoshi Watanabe ,  Yasushi Kasa

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C7/06 ,  G11C16/06 ,  G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  H01L21/8247 ,  H01L27/115

CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C2029/5006

摘要： An object of the present invention is to provided a semiconductor device that permits easy and efficient testing. A semiconductor device which is characterized in that the power supply for an output circuit is selectable between a normal power supply and an independent power supply provided independently of the normal supply.

摘要翻译： 本发明的目的是提供一种允许容易和有效测试的半导体器件。 一种半导体器件，其特征在于，用于输出电路的电源可在普通电源和独立于正常供电设置的独立电源之间进行选择。

公开(公告)号：US5149990A

公开(公告)日：1992-09-22

申请号：US642837

申请日：1991-01-18

申请人： Hirokazu Yamazaki ,  Masanobu Yoshida

发明人： Hirokazu Yamazaki ,  Masanobu Yoshida

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  H01L21/822 ,  H01L27/04 ,  H03K5/00 ,  H03K19/003

CPC分类号： G11C8/18 ,  G11C7/22 ,  H03K19/00361

摘要： A semiconductor device for absorbing a noise comprises a first and second buffer. The first and second buffers receive an external signal having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first buffer, which issues an output signal for controlling the internal circuits of a chip of the semiconductor device so as to make the chip's internal circuits active/stand-by, is not sensitive to the rising edge of the external signal, but is sensitive to the falling edge of the same external signal. The second buffer, which issues an output signal for controlling an output circuit of a chip of the semiconductor device so as to make the output circuit active/stand-by, is sensitive to both the rising and the falling edges of the external signal.

公开(公告)号：US06229728B1

公开(公告)日：2001-05-08

申请号：US09296544

申请日：1999-04-22

申请人： Chikai Ono ,  Hirokazu Yamazaki

发明人： Chikai Ono ,  Hirokazu Yamazaki

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric memory includes memory cells, a pair of bit lines to which the memory cells are connected, and a control circuit which changes a reference cell applied to one of the pair of bit lines while data read from one of the memory cells is output to the other one of the pair of bit lines.

摘要翻译： 铁电存储器包括存储器单元，存储单元连接到的一对位线，以及控制电路，其将从一个存储单元读取的数据输出到对应于一对位线之一的参考单元， 另一个位线对。