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15 条记录 (耗时 0.027 秒)

    Semiconductor memory device including programmable mode selection circuitry
    1.
    发明授权
    Semiconductor memory device including programmable mode selection circuitry 失效
    半导体存储器件包括可编程模式选择电路

    公开(公告)号：US4833650A

    公开(公告)日：1989-05-23

    申请号：US34094

    申请日：1987-04-02

    申请人： Kazutoshi Hirayama ,  Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Hideto Hidaka

    发明人： Kazutoshi Hirayama ,  Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Hideto Hidaka

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

    CPC分类号： G11C7/22 ,  G11C11/4096 ,  G11C7/1033 ,  G11C7/1045

    摘要： A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.

    摘要翻译： 半导体存储器件包括设置在该器件的存储器芯片上的多个操作模式控制电路，用于分别执行至少包括静态列模式，高速页模式和半字节模式的对应多个写/读操作模式， 以及设置在所述存储芯片上的多个操作模式选择电路，每个所述操作模式选择电路具有熔丝元件和用于在所述熔丝元件被切断时选择所述多个所述操作模式控制电路中的一个的焊盘， 接合焊盘是有选择地布线的，从而可以在同一芯片上选择性地实现各种功能。

    Semiconductor memory device performing multi-bit Serial operation
    3.
    发明授权
    Semiconductor memory device performing multi-bit Serial operation 失效
    半导体存储器件执行多位串行操作

    公开(公告)号：US4835743A

    公开(公告)日：1989-05-30

    申请号：US92615

    申请日：1987-09-03

    申请人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Kazutoshi Hirayama

    发明人： Hideto Hidaka ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Kazutoshi Hirayama

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409

    CPC分类号： G11C7/1033

    摘要： In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

    摘要翻译： 在能够进行半字节模式操作的半导体存储器件中，从正常模式时和在上一时刻起，当＆amp; C＆gt;信号下降到数据输出缓冲器激活信号上升时的时间所需的时间段变得不同 半字节模式，因此与常规设备相比，读取半字节模式中的数据所需的时间段被减少。

    Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire
    4.
    发明授权
    Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire 失效
    内部电压发生电路，半导体存储器件和测量电流消耗的方法，能够在不切割电线的情况下测量电流消耗

    公开(公告)号：US5835434A

    公开(公告)日：1998-11-10

    申请号：US587684

    申请日：1996-01-17

    申请人： Kazutoshi Hirayama

    发明人： Kazutoshi Hirayama

    IPC分类号： G11C11/407 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

    CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C5/146 ,  G11C11/401 ,  G11C2029/5006

    摘要： This substrate voltage generating circuit (internal voltage generating circuit) includes an oscillator, a p channel transistor, an AND circuit, and a pump circuit. The substrate voltage generating circuit is stopped by applying stop signals S and S to the p channel transistor and the AND circuit connected to the oscillator, and by cutting supply of power supply voltage to the oscillator and a path of output of the oscillator. In order to find current consumption at stand-by of a semiconductor memory device, current consumptions of the whole semiconductor memory device at stand-by before and after operation of the substrate voltage generating circuit is stopped as described above are measured, and the difference between them is calculated. Current consumption of the substrate voltage generating circuit is thus found. As described above, the internal voltage generating circuit can be stopped without cutting a wire, thereby allowing measurement of current consumption of the internal voltage generating circuit at stand-by of the semiconductor memory device. As a result, a problem caused by cutting of the wire can be prevented.

    摘要翻译： 该衬底电压产生电路（内部电压产生电路）包括振荡器，p沟道晶体管，AND电路和泵电路。 通过向p沟道晶体管施加停止信号S和+ E，ovs S + EE以及连接到振荡器的AND电路，并通过切断对振荡器的电源电压和输出路径来停止衬底电压产生电路 的振荡器。 为了在半导体存储器件的待机中寻找电流消耗，如上所述测量基板电压产生电路的操作之前和之后待机的整个半导体存储器件的电流消耗被停止，并且 他们是计算的。 因此发现了基板电压产生电路的电流消耗。 如上所述，可以停止内部电压产生电路而不切断线，从而允许在半导体存储器件待机时测量内部电压产生电路的电流消耗。 结果，可以防止由切割线引起的问题。

    Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same
    5.
    发明授权
    Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same 失效
    半导体存储器件包括以不同访问速度操作的两种存储器单元及其操作和制造方法

    公开(公告)号：US5663905A

    公开(公告)日：1997-09-02

    申请号：US469161

    申请日：1995-06-06

    申请人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

    发明人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

    IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/401 ,  H01L27/10 ,  H01L27/105 ,  G11C11/24

    CPC分类号： H01L27/105 ,  G11C11/005

    摘要： A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

    摘要翻译： 半导体存储器件包括动态存储单元阵列，静态存储单元阵列，多个字线，多个DRAM位线对和多个SRAM位线对。 动态存储单元阵列包括以矩阵形状排列的多个动态存储单元。 静态存储单元阵列被布置成与动态存储单元阵列相邻。 静态存储单元阵列包括以矩阵形状排列的静态存储单元。 多个字线被布置成多行。 每个字线连接到布置在相应行中的动态和静态存储单元。 多个DRAM位线对排列成多列。 每个DRAM位线对连接到动态存储单元。 在其他多个列中布置有多个SRAM位线对。 每个SRAM位线对连接到布置在相应列中的静态存储单元。

    Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same
    6.
    发明授权
    Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same 失效
    半导体存储器件包括以不同访问速度操作的两种存储器单元及其操作和制造方法

    公开(公告)号：US5781468A

    公开(公告)日：1998-07-14

    申请号：US851757

    申请日：1997-05-06

    申请人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

    发明人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

    IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/401 ,  H01L27/10 ,  H01L27/105 ,  G11C11/24

    CPC分类号： H01L27/105 ,  G11C11/005

    摘要： A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

    摘要翻译： 半导体存储器件包括动态存储单元阵列，静态存储单元阵列，多个字线，多个DRAM位线对和多个SRAM位线对。 动态存储单元阵列包括以矩阵形状排列的多个动态存储单元。 静态存储单元阵列被布置成与动态存储单元阵列相邻。 静态存储单元阵列包括以矩阵形状排列的静态存储单元。 多个字线被布置成多行。 每个字线连接到布置在相应行中的动态和静态存储单元。 多个DRAM位线对排列成多列。 每个DRAM位线对连接到动态存储单元。 在其他多个列中布置有多个SRAM位线对。 每个SRAM位线对连接到布置在相应列中的静态存储单元。

    Semiconductor memory device with precharging voltage level unchanged by defective memory cell
    8.
    发明授权
    Semiconductor memory device with precharging voltage level unchanged by defective memory cell 失效
    半导体存储器件，具有由缺陷存储单元不变的预充电电压电平

    公开(公告)号：US5315551A

    公开(公告)日：1994-05-24

    申请号：US651855

    申请日：1991-02-07

    申请人： Kazutoshi Hirayama

    发明人： Kazutoshi Hirayama

    IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04

    CPC分类号： G11C29/84 ,  G11C29/832

    摘要： A semiconductor memory device having a redundant circuit for electrically replacing a defective memory cell column with a spare memory cell column. An electric fuse (25) is connected between a precharging voltage line (V.sub.BL) and bit lines (BL, BL). When a defective memory cell exists, the precharging voltage tries to vary through this fuse. However, this fuse is cut off, so that the precharging voltage is prevented from varying. Accordingly, data stored in the remaining memory cells are read out correctly and without delay.

    摘要翻译： 一种具有冗余电路的半导体存储器件，用于用备用存储单元列电替换有缺陷的存储单元列。 电气保险丝（25）连接在预充电电压线（VBL）和位线（BL，＆amp; B和B）之间。 当有缺陷的存储单元存在时，预充电电压试图通过该保险丝变化。 然而，该保险丝被切断，从而防止预充电电压变化。 因此，正确地且没有延迟地读出存储在剩余存储单元中的数据。