公开(公告)号：US20090218572A1

公开(公告)日：2009-09-03

申请号：US12390954

申请日：2009-02-23

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78669

摘要： A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.

摘要翻译： 解决了导通状态电流和截止电流的问题的薄膜晶体管，以及能够进行高速运转的薄膜晶体管。 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极和漏极区域，其间具有间隔，以便与具有栅极绝缘层的栅电极重叠 插入在栅电极和杂质半导体层之间; 添加作为受体的杂质元素的一对半导体层，与栅极电极和杂质半导体层重叠在栅极绝缘层上，并且在沟道长度方向上间隔设置; 以及与所述栅绝缘层和所述一对半导体层接触并在所述一对半导体层之间延伸的非晶半导体层。

公开(公告)号：US20090114917A1

公开(公告)日：2009-05-07

申请号：US12263702

申请日：2008-11-03

申请人： Shunpei YAMAZAKI ,  Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO

发明人： Shunpei YAMAZAKI ,  Satoshi KOBAYASHI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO

IPC分类号： H01L29/04

CPC分类号： H01L29/04 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes a gate electrode, a gate insulating layer covering the gate electrode, a microcrystalline semiconductor layer over the gate insulating layer, an amorphous semiconductor layer over the microcrystalline semiconductor layer, source and drain regions over the amorphous semiconductor layer, source and drain electrodes in contact with and over the source and drain regions, and a part of the amorphous semiconductor layer overlapping with the source and drain regions is thicker than a part of the amorphous semiconductor layer overlapping with a channel formation region. The side face of the source and drain regions and the side face of the amorphous semiconductor form a tapered shape together with an outmost surface of the amorphous semiconductor layer. The taper angle of the tapered shape is such an angle that decrease electric field concentration around a junction portion between the source and drain regions and the amorphous semiconductor layer.

摘要翻译： 薄膜晶体管包括栅电极，覆盖栅电极的栅极绝缘层，栅极绝缘层上的微晶半导体层，微晶半导体层上的非晶半导体层，非晶半导体层上的源极和漏极区，源极和 与源极和漏极区域接触和超过的漏极电极，与源极和漏极区域重叠的部分非晶半导体层比与沟道形成区域重叠的非晶半导体层的一部分更厚。 源极和漏极区域的侧面和非晶半导体的侧面与非晶半导体层的最外表面一起形成锥形形状。 锥形形状的锥角是减小源极和漏极区域与非晶半导体层之间的接合部周围的电场浓度的角度。

公开(公告)号：US20110248268A1

公开(公告)日：2011-10-13

申请号：US13167762

申请日：2011-06-24

申请人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US20100148178A1

公开(公告)日：2010-06-17

申请号：US12633021

申请日：2009-12-08

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/78669 ,  H01L27/12 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78678 ,  H01L29/78696

摘要： A thin film transistor includes: a gate electrode layer; a first semiconductor layer; a second semiconductor layer having lower carrier mobility than the first semiconductor layer, which is provided over and in contact with the first semiconductor layer; a gate insulating layer which is provided between and in contact with the gate electrode layer and the first semiconductor layer; first impurity semiconductor layers which are provided so as to be in contact with the second semiconductor layer; second impurity semiconductor layers which are provided so as to be partially in contact with the first impurity semiconductor layers and the first and second semiconductor layers; and source and drain electrode layers which are provided so as to be in contact with entire surfaces of the second impurity semiconductor layers, in which an entire surface of the first semiconductor layer on the gate electrode layer side overlaps with the gate electrode layer.

摘要翻译： 薄膜晶体管包括：栅极电极层; 第一半导体层; 具有比所述第一半导体层低的载流子迁移率的第二半导体层，其设置在所述第一半导体层上并与其接触; 栅极绝缘层，设置在栅电极层和第一半导体层之间并与栅电极层和第一半导体层接触; 设置为与第二半导体层接触的第一杂质半导体层; 第二杂质半导体层，其设置成部分地与第一杂质半导体层以及第一和第二半导体层接触; 以及源极和漏极电极层，其设置成与第二杂质半导体层的整个表面接触，其中栅极电极层侧的第一半导体层的整个表面与栅极电极层重叠。

公开(公告)号：US20100148175A1

公开(公告)日：2010-06-17

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US20090218568A1

公开(公告)日：2009-09-03

申请号：US12391398

申请日：2009-02-24

申请人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Takayuki IKEDA ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Daisuke KAWAE ,  Takayuki INOUE ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786 ,  H01L33/00

CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

摘要翻译： 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

公开(公告)号：US20120193620A1

公开(公告)日：2012-08-02

申请号：US13358556

申请日：2012-01-26

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Masashi TSUBUKU

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Masashi TSUBUKU

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/42384

摘要： A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.

摘要翻译： 可以提供耐受高电压并控制大电力的晶体管。 提供一种晶体管，其包括栅电极，栅电极上的栅极绝缘层，栅极绝缘层上方并与栅电极重叠的氧化物半导体层，以及与栅电极接触的源电极和漏电极 氧化物半导体层，其端部与栅电极重叠。 栅极绝缘层包括与漏电极的端部重叠的第一区域和与第一区域相邻的第二区域。 第一区域具有比第二区域小的电容。

公开(公告)号：US20120104385A1

公开(公告)日：2012-05-03

申请号：US13279868

申请日：2011-10-24

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/78648

摘要： A semiconductor device includes a first gate electrode; a gate insulating layer covering the first gate electrode; an oxide semiconductor layer that overlaps with the first gate electrode; oxide semiconductor layers having high carrier density covering end portions of the oxide semiconductor layer; a source electrode and a drain electrode in contact with the oxide semiconductor layers having high carrier density; an insulating layer covering the source electrode, the drain electrode, and the oxide semiconductor layer; and a second gate electrode that is in contact with the insulating layer. Each of the oxide semiconductor layers is in contact with part of each of an upper surface, a lower surface, and a side surface of one of the end portions of the oxide semiconductor layer and part of an upper surface of the gate insulating layer.

摘要翻译： 半导体器件包括第一栅电极; 覆盖所述第一栅电极的栅极绝缘层; 与所述第一栅电极重叠的氧化物半导体层; 具有覆盖氧化物半导体层的端部的高载流子密度的氧化物半导体层; 与具有高载流子密度的氧化物半导体层接触的源电极和漏电极; 覆盖源电极，漏电极和氧化物半导体层的绝缘层; 以及与绝缘层接触的第二栅电极。 每个氧化物半导体层与氧化物半导体层的一个端部和栅极绝缘层的上表面的一部分的上表面，下表面和侧表面的一部分接触。

公开(公告)号：US20120061662A1

公开(公告)日：2012-03-15

申请号：US13220992

申请日：2011-08-30

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Satoshi KOBAYASHI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Satoshi KOBAYASHI

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/78648

摘要： An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

摘要翻译： 本发明的目的是提供具有诸如高耐受电压，低反向饱和电流和高导通电流等电特性的半导体器件。 特别地，目的是提供一种包括非线性元件的功率二极管和整流器。 本发明的一个实施例是一种半导体器件，包括第一电极，覆盖第一电极的栅极绝缘层，与栅极绝缘层接触并与第一电极重叠的氧化物半导体层，覆盖端部的一对第二电极 所述氧化物半导体层的绝缘层，覆盖所述一对第二电极和所述氧化物半导体层的绝缘层，以及与所述绝缘层和所述一对第二电极接触的第三电极。 一对第二电极与氧化物半导体层的端面接触。

公开(公告)号：US20090218576A1

公开(公告)日：2009-09-03

申请号：US12390144

申请日：2009-02-20

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI ,  Hiromichi GODO ,  Daisuke KAWAE ,  Satoshi KOBAYASHI

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L27/1214 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.

摘要翻译： 薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于 栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅极电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上间隔开; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。