公开(公告)号：US20120193620A1

公开(公告)日：2012-08-02

申请号：US13358556

申请日：2012-01-26

申请人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Masashi TSUBUKU

发明人： Hiromichi GODO ,  Satoshi KOBAYASHI ,  Masashi TSUBUKU

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/42384

摘要： A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.

摘要翻译： 可以提供耐受高电压并控制大电力的晶体管。 提供一种晶体管，其包括栅电极，栅电极上的栅极绝缘层，栅极绝缘层上方并与栅电极重叠的氧化物半导体层，以及与栅电极接触的源电极和漏电极 氧化物半导体层，其端部与栅电极重叠。 栅极绝缘层包括与漏电极的端部重叠的第一区域和与第一区域相邻的第二区域。 第一区域具有比第二区域小的电容。

公开(公告)号：US20110062435A1

公开(公告)日：2011-03-17

申请号：US12880286

申请日：2010-09-13

申请人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Hiromichi GODO

发明人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Hiromichi GODO

IPC分类号： H01L29/12 ,  H01L21/16

CPC分类号： H01L29/7869

摘要： It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 μm to 100 μm inclusive, preferably 3 μm to 10 μm inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or −25° C. to −150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.

摘要翻译： 本发明的目的是提供具有稳定电特性的高可靠性薄膜晶体管，其包括氧化物半导体膜。 包含氧化物半导体膜的薄膜晶体管的沟道长度在1.5μm〜100μm的范围内，优选为3μm〜10μm; 当在室温至180℃的操作温度范围或-25℃至-150℃的操作温度范围内，阈值电压的变化量小于或等于3V，优选小于或等于1.5V 包括在内，可以制造具有稳定电特性的半导体器件。 特别地，在作为半导体器件的实施例的显示装置中，可以降低由于阈值电压的变化引起的显示不均匀。

公开(公告)号：US20120299003A1

公开(公告)日：2012-11-29

申请号：US13568186

申请日：2012-08-07

申请人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Atsushi HIROSE ,  Masashi TSUBUKU ,  Kosei NODA

IPC分类号： H01L29/22 ,  H01L27/15 ,  H01L29/786

CPC分类号： H01L27/1225 ,  H01L21/823412 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/156 ,  H01L27/3213 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7869 ,  H01L29/78693 ,  H01L33/025 ,  H01L2924/0002 ,  H04M1/0266 ,  H04R1/02 ,  H01L2924/00

摘要： An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

摘要翻译： 目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。 使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用 其中不产生电场。 因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

公开(公告)号：US20120138922A1

公开(公告)日：2012-06-07

申请号：US13307398

申请日：2011-11-30

申请人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

发明人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

IPC分类号： H01L29/12

CPC分类号： H01L29/78696 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

摘要： An oxide semiconductor film which has more stable electric conductivity is provided. Further, a semiconductor device which has stable electric characteristics and high reliability is provided by using the oxide semiconductor film. An oxide semiconductor film includes a crystalline region, and the crystalline region includes a crystal in which an a-b plane is substantially parallel with a surface of the film and a c-axis is substantially perpendicular to the surface of the film; the oxide semiconductor film has stable electric conductivity and is more electrically stable with respect to irradiation with visible light, ultraviolet light, and the like. By using such an oxide semiconductor film for a transistor, a highly reliable semiconductor device having stable electric characteristics can be provided.

摘要翻译： 提供了具有更稳定的导电性的氧化物半导体膜。 此外，通过使用氧化物半导体膜提供具有稳定的电特性和高可靠性的半导体器件。 氧化物半导体膜包括结晶区域，并且结晶区域包括其中a-b平面基本上平行于膜的表面并且c轴基本上垂直于膜的表面的晶体; 氧化物半导体膜具有稳定的导电性，并且相对于可见光，紫外线等的照射而言更加电稳定。 通过使用这种用于晶体管的氧化物半导体膜，可以提供具有稳定电特性的高可靠性半导体器件。

公开(公告)号：US20110318916A1

公开(公告)日：2011-12-29

申请号：US13228486

申请日：2011-09-09

申请人： Kengo AKIMOTO ,  Masashi TSUBUKU

发明人： Kengo AKIMOTO ,  Masashi TSUBUKU

IPC分类号： H01L21/283

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/41733

摘要： An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer.

摘要翻译： 即使在形成了栅极绝缘层，源极电极层和漏极电极层之后形成氧化物半导体，也是要抑制元件特性的劣化。 在基板上形成栅极电极层。 在栅电极层上形成栅极绝缘层。 源极电极层和漏电极层形成在栅绝缘层上。 在形成在基板上的栅极绝缘层，源极电极层和漏极电极层的表面上进行表面处理。 在进行表面处理之后，在栅极绝缘层，源极电极层和漏极电极层上形成氧化物半导体层。

公开(公告)号：US20110204362A1

公开(公告)日：2011-08-25

申请号：US13026518

申请日：2011-02-14

申请人： Kengo AKIMOTO ,  Ryosuke WATANABE ,  Masashi TSUBUKU ,  Shunpei YAMAZAKI

发明人： Kengo AKIMOTO ,  Ryosuke WATANABE ,  Masashi TSUBUKU ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618

摘要： It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.

摘要翻译： 本发明的目的是提供一种包括氧化物半导体的半导体器件，其中实现了晶体管的小型化和电场的集中。 栅电极的宽度减小，源电极层和漏电极层之间的间隔缩短。 通过使用栅电极作为掩模以自对准的方式添加稀有气体，可以在氧化物半导体层中提供与沟道形成区域接触的低电阻区域。 因此，即使栅电极的宽度，即栅极配线的线宽小，也能够提供高电位区域的高位置精度，能够实现晶体管的小型化。

公开(公告)号：US20110059575A1

公开(公告)日：2011-03-10

申请号：US12871122

申请日：2010-08-30

申请人： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

发明人： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

IPC分类号： H01L21/34

CPC分类号： H01L27/1262 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

摘要： It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

摘要翻译： 本发明的目的是提供一种包括氧化物半导体膜的薄膜晶体管的结构的制造方法，其中形成沟道的阈值电压为正且尽可能接近0V。 形成保护绝缘层以覆盖包括通过第一热处理脱水或脱氢的氧化物半导体层的薄膜晶体管，以及在比第一热处理低的温度下进行第二热处理，其中， 重复多次温度的降低，由此，在不影响通道长度的情况下，包含氧化物半导体层的薄膜晶体管，其中形成沟道的阈值电压为正且尽可能接近0V，可以 制造。

公开(公告)号：US20110024740A1

公开(公告)日：2011-02-03

申请号：US12846572

申请日：2010-07-29

申请人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Junichiro SAKATA

发明人： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Junichiro SAKATA

IPC分类号： H01L29/786 ,  H01L21/44

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L29/7869

摘要： A semiconductor device having a structure which enables sufficient reduction in parasitic capacitance is provided. In addition, the operation speed of thin film transistors in a driver circuit is improved. In a bottom-gate thin film transistor in which an oxide insulating layer is in contact with a channel formation region in an oxide semiconductor layer, a source electrode layer and a drain electrode layer are formed in such a manner that they do not overlap with a gate electrode layer. Thus, the distance between the gate electrode layer and the source electrode layer and between the gate electrode layer and the drain electrode layer are increased; accordingly, parasitic capacitance can be reduced.

摘要翻译： 提供具有能够充分降低寄生电容的结构的半导体器件。 此外，提高了驱动电路中薄膜晶体管的操作速度。 在其中氧化物绝缘层与氧化物半导体层中的沟道形成区域接触的底栅极薄膜晶体管中，以与栅极薄膜晶体管不重叠的方式形成源电极层和漏电极层， 栅电极层。 因此，栅极电极层与源电极层之间以及栅极电极层和漏极电极层之间的距离增加; 因此，可以减小寄生电容。

公开(公告)号：US20120061663A1

公开(公告)日：2012-03-15

申请号：US13226713

申请日：2011-09-07

申请人： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

发明人： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC分类号： H01L29/12 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

摘要： An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

摘要翻译： 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US20110210325A1

公开(公告)日：2011-09-01

申请号：US12871148

申请日：2010-08-30

申请人： Masayuki SAKAKURA ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA

发明人： Masayuki SAKAKURA ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/124 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2202/10 ,  H01L27/1225 ,  H01L27/1255

摘要： The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

摘要翻译： 半导体器件包括驱动器电路部分，其包括驱动器电路和包括像素的像素部分。 像素包括具有透光性的栅极电极层，栅极绝缘层，源极电极层和漏极电极层，其各自具有设置在栅极绝缘层上的透光性，覆盖顶表面的氧化物半导体层和 源极电极层和漏极电极层的侧面，并且在栅电极层之间设置有栅极绝缘层，导电层设置在氧化物半导体层的一部分上，并且具有比源电极层和漏极 电极层和与氧化物半导体层的一部分接触的氧化物绝缘层。