公开(公告)号：US5126905A

公开(公告)日：1992-06-30

申请号：US551474

申请日：1990-07-12

申请人： Hironori Nomura ,  Masao Morimoto ,  Hitoshi Kurihara

发明人： Hironori Nomura ,  Masao Morimoto ,  Hitoshi Kurihara

IPC分类号： G11B21/02 ,  G11B21/08

CPC分类号： G11B21/08

摘要： In a data writing and/or reading device in which data is written and/or read out from a rotating recording medium, a head carriage upon which one or more heads are mounted is guided by first and second guide rods to move in a predetermined direction with respect to the recording medium. A member for biasing the head carriage in the direction opposite the direction of a rotating force produced by the friction between the head or heads and the recording medium is provided. This force in the direction of rotation of the recording medium is counteracted so that deviation of the head in the direction of rotation of the recording medium is eliminated.

摘要翻译： 在从旋转记录介质写入和/或读取数据的数据写入和/或读取装置中，安装有一个或多个磁头的磁头托架由第一和第二导向杆引导以沿预定方向移动 相对于记录介质。 提供了一种用于沿与头部或头部与记录介质之间的摩擦产生的旋转力的方向相反的方向偏压头部托架的构件。 抵消记录介质的旋转方向的这种力，从而消除了磁头在记录介质旋转方向上的偏差。

公开(公告)号：US5241437A

公开(公告)日：1993-08-31

申请号：US720370

申请日：1991-06-25

申请人： Masao Morimoto ,  Hironori Nomura

发明人： Masao Morimoto ,  Hironori Nomura

IPC分类号： G11B5/48

CPC分类号： G11B5/4826

摘要： In a signal recording and/or reproducing device having a chassis, a read/write head assembly includes a read/write head for sliding in contact with a surface of a moving flexible recording medium and for reading information from and writing information onto the surface of the moving flexible recording medium, and a head supporting plate for elastically supporting the read/write head. The head supporting plate includes a first supporting frame for mounting the read/write head, a second supporting frame elastically connected to the first supporting frame by a first pair of tie bar portions, and a third supporting frame for fixing the head supporting plate to the chassis of the recording and/or reproducing device. The third supporting frame is elastically connected to the second supporting frame by a second pair of tie bar portions. Connecting points between the first pair of tie bar portions and the first supporting frame mounting the read/write head are disposed nearer a trailing side of the read/write head with respect to a direction of movement of the recording medium than connecting points between the first pair of tie bar portions and the second supporting frame.

摘要翻译： 在具有底盘的信号记录和/或再现装置中，读/写头组件包括读/写头，用于与移动的柔性记录介质的表面滑动滑动，并用于从信息记录和/ 移动的柔性记录介质和用于弹性地支撑读/写头的头支撑板。 头支撑板包括用于安装读/写头的第一支撑框架，通过第一对连杆部分弹性地连接到第一支撑框架的第二支撑框架和用于将头支撑板固定到第二支撑框架的第三支撑框架 记录和/或再现装置的底盘。 第三支撑框架通过第二对连接杆部分弹性连接到第二支撑框架。 安装读/写头的第一对连杆部分和第一支撑框架之间的连接点相对于记录介质的移动方向设置在读/写头的后侧，而不是位于第一 一对拉杆部分和第二支撑框架。

公开(公告)号：US5257255A

公开(公告)日：1993-10-26

申请号：US921439

申请日：1992-07-31

申请人： Masao Morimoto ,  Hitoshi Kurihara ,  Ryuichi Negishi ,  Toru Okada ,  Masae Ikeda

发明人： Masao Morimoto ,  Hitoshi Kurihara ,  Ryuichi Negishi ,  Toru Okada ,  Masae Ikeda

IPC分类号： G11B5/55 ,  G11B19/00 ,  G11B19/02 ,  G11B33/08 ,  G11B19/04 ,  G11B27/36

CPC分类号： G11B33/08 ,  G11B19/00 ,  G11B19/02 ,  G11B5/5521 ,  G11B5/5582

摘要： A head for writing data into and/or reading data out of a recording medium such as a magnetic disc is displaced along a path by a motor such as a voice coil motor. The moving member of the motor is disposed on one side of the path, and another moving member of a speed sensor for detecting the head displacement speed is disposed on the opposite side. As a result, an unbalanced mass arrangement with respect to the path along which the head is displaced will not occur. The signal from the speed sensor can be used, for example, to interrupt a write operation if a mechanical impact occurs. Furthermore, even in an embodiment in which a coil is wound around the moving member of the speed sensor so that the head displacement speed is detected as a voltage induced across the coil as the head is displaced, the motor and the speed sensor are disposed in spaced-apart-relationship with each other and the speed sensor is less susceptible to adverse effects caused by the leakage flux from the motor.

摘要翻译： 用于将数据写入和/或从诸如磁盘的记录介质读取数据的磁头通过诸如音圈电动机之类的电动机沿着路径移位。 电动机的移动部件设置在路径的一侧，并且用于检测头位移速度的速度传感器的另一个移动部件设置在相对侧。 结果，不会发生相对于头部移位的路径的不平衡质量布置。 例如，如果发生机械冲击，来自速度传感器的信号可以用于中断写入操作。 此外，即使在将线圈卷绕在速度传感器的移动部件上的一个实施例中，使得头部位移速度被检测为当头部移位时在线圈上感应出的电压，马达和速度传感器被设置在 彼此间隔开的关系，速度传感器不易受到来自马达的漏磁通的不利影响。

公开(公告)号：USRE30851E

公开(公告)日：1982-01-19

申请号：US125749

申请日：1980-02-28

申请人： Kenzo Toda ,  Hisashi Gondo ,  Bunichiro Kawasaki ,  Mitsunobu Abe ,  Ryoseki Katsutani ,  Tsuyoshi Kawano ,  Norimasa Uehara ,  Yoshio Saito ,  Kenichiro Suemune ,  Masahiko Shiraishi ,  Yoshifumi Tadashige ,  Masao Morimoto ,  Takao Tsukamura ,  Kurayoshi Watanabe ,  Teruhiko Nishimura

发明人： Kenzo Toda ,  Hisashi Gondo ,  Bunichiro Kawasaki ,  Mitsunobu Abe ,  Ryoseki Katsutani ,  Tsuyoshi Kawano ,  Norimasa Uehara ,  Yoshio Saito ,  Kenichiro Suemune ,  Masahiko Shiraishi ,  Yoshifumi Tadashige ,  Masao Morimoto ,  Takao Tsukamura ,  Kurayoshi Watanabe ,  Teruhiko Nishimura

IPC分类号： B21B1/22 ,  B21B15/00 ,  B21B31/10 ,  B21B39/08 ,  C21D8/04 ,  C21D9/52 ,  C21D9/56 ,  C21D9/573

CPC分类号： C21D8/0426 ,  B21B31/10 ,  C21D8/0452 ,  C21D8/0473 ,  C21D9/52 ,  C21D9/56 ,  B21B2001/228 ,  B21B2015/0071 ,  B21B39/08 ,  C21D8/0436 ,  C21D8/0442 ,  C21D9/563 ,  C21D9/573

摘要： In the production of low-carbon steel, particularly low-carbon steel sheet containing less than 0.25% of Mn, improvements in the method and apparatus, which comprises hot rolling a steel having a controlled range content of Mn, O and S contents, then coiling thus hot rolled steel at temperatures between 600.degree.-800.degree. C., further cold rolling the hot rolled plate down to a prescribed thickness, annealing and overaging the steel in a continuous furnace, rapidly cooling the steel near room temperatures and skin pass rolling, leveling, and recoiling the sheet. Thus produced steel sheet is very useful for applications such as pressed automobile body parts which require good workability particularly good drawability.

公开(公告)号：US20130026580A1

公开(公告)日：2013-01-31

申请号：US13559461

申请日：2012-07-26

申请人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

发明人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC分类号： H01L27/11

CPC分类号： H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

摘要： A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

摘要翻译： 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US08125845B2

公开(公告)日：2012-02-28

申请号：US12687339

申请日：2010-01-14

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

IPC分类号： G11C7/00

CPC分类号： G11C11/413 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227

摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.

摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

公开(公告)号：US08854869B2

公开(公告)日：2014-10-07

申请号：US12855691

申请日：2010-08-12

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C5/06 ,  G11C11/413

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US20110063895A1

公开(公告)日：2011-03-17

申请号：US12855691

申请日：2010-08-12

申请人： Shigenobu KOMATSU ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

发明人： Shigenobu KOMATSU ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC分类号： G11C11/417 ,  G11C11/412 ,  G11C5/14

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US08957459B2

公开(公告)日：2015-02-17

申请号：US13559461

申请日：2012-07-26

申请人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

发明人： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L27/02 ,  G11C11/412

CPC分类号： H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

摘要： A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

摘要翻译： 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US07569690B2

公开(公告)日：2009-08-04

申请号：US10524517

申请日：2003-09-02

申请人： Masao Morimoto ,  Haruyo Sato

发明人： Masao Morimoto ,  Haruyo Sato

IPC分类号： C07D241/04 ,  C07D295/00

CPC分类号： C07D295/205

摘要： If an organic solvent with a water content of 15% or less is used when an oxycarbonyl-substituted piperazine derivative is produced from a piperazine derivative, the piperazine derivative can be oxycarbonylated.

摘要翻译： 当由哌嗪衍生物生成氧羰基取代的哌嗪衍生物时，如果使用含水率为15％以下的有机溶剂，则可以将哌嗪衍生物进行氧羰基化。