公开(公告)号：US06651152B1

公开(公告)日：2003-11-18

申请号：US09504727

申请日：2000-02-16

申请人： Hiroshi Ueki ,  Teruaki Kanzaki

发明人： Hiroshi Ueki ,  Teruaki Kanzaki

IPC分类号： G06F1300

CPC分类号： G06F9/445

摘要： A microcomputer system having a central processor, a plurality of memory types and a bus interface circuit is configured to allow an external device to download and upload data to/from the various memories using a download circuit connected to the plurality of memories via the bus interface circuit. In operation, a first reset signal, a second reset signal and a mode set signal operate to control whether the central processor or the download circuit will be active, and whether a selector will couple the central processing unit or the download circuit to the bus interface circuit.

摘要翻译： 具有中央处理器，多个存储器类型和总线接口电路的微计算机系统被配置为允许外部设备使用经由总线接口连接到多个存储器的下载电路来下载和向各种存储器上载数据 电路。 在操作中，第一复位信号，第二复位信号和模式设置信号操作以控制中央处理器或下载电路是否将被激活，以及选择器是否将中央处理单元或下载电路耦合到总线接口 电路。

公开(公告)号：US08178981B2

公开(公告)日：2012-05-15

申请号：US12715925

申请日：2010-03-02

申请人： Teruaki Kanzaki ,  Yoshinori Deguchi ,  Kazunobu Miki

发明人： Teruaki Kanzaki ,  Yoshinori Deguchi ,  Kazunobu Miki

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4899 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： The present invention aims at offering the semiconductor device which can improve the strength to the stress generated with a bonding pad. In the semiconductor device concerning the present invention, a plurality of bonding pads are formed on a semiconductor chip. In each bonding pad, a plurality of second line-like metals are formed under the first metal formed using the wiring layer of the top layer. And a bonding pad is put in order and located along the long-side direction of a second metal to achieve the above objects. That is, a bonding pad is put in order and located so that the long-side direction of a second metal and the arrangement direction of a bonding pad may become in the same direction.

摘要翻译： 本发明的目的在于提供一种半导体器件，其能够提高由焊盘产生的应力的强度。 在本发明的半导体装置中，在半导体芯片上形成有多个接合焊盘。 在每个接合焊盘中，在使用顶层的布线层形成的第一金属之下形成多个第二线状金属。 并且沿着第二金属的长边方向依次放置接合焊盘，以实现上述目的。 也就是说，依次放置焊盘，使得第二金属的长边方向和焊盘的排列方向可以变成相同的方向。

公开(公告)号：US5983018A

公开(公告)日：1999-11-09

申请号：US75824

申请日：1998-05-12

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： G06F11/28 ,  G06F9/48 ,  G06F11/36 ,  G06F9/44 ,  G06F11/00

CPC分类号： G06F11/362

摘要： A microcomputer for checking a flag in a flag circuit to determine whether or not to decrement a count of a program counter. If the flag indicates execution of a STOP instruction, the program counter value is decremented so that the address of a destination to return to at the end of debug interrupt handling is replaced by the address of the STOP instruction. If the flag gives any other indication, the program counter value is used unchanged as the return destination address that will be in effect at the end of debug interrupt handling.

摘要翻译： 一种用于检查标志电路中的标志以确定是否减少程序计数器的计数的微计算机。 如果标志指示执行STOP指令，则程序计数器值递减，以便在调试中断处理结束时返回的目标地址由STOP指令的地址替换。 如果标志给出任何其他指示，则程序计数器值将不变地用作在调试中断处理结束时将生效的返回目标地址。

公开(公告)号：US08067961B2

公开(公告)日：2011-11-29

申请号：US12634608

申请日：2009-12-09

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

摘要翻译： 在电平转换电路中，两个P沟道MOS晶体管形成电流镜电路。 当输入信号从“L”电平上升到“H”电平时，连接到一个P沟道MOS晶体管的漏极的N沟道MOS晶体管导通，以防止漏电流流过两个P沟道MOS 晶体管，这降低了功耗。 此外，当输入信号从“L”电平上升到“H”电平时，连接到另一个P沟道MOS晶体管的漏极的P沟道MOS晶体管导通，以固定其中的一个节点的电位 另一个P沟道MOS晶体管的漏极为“H”电平，从而防止节点的电位变得不稳定。

公开(公告)号：US07656201B2

公开(公告)日：2010-02-02

申请号：US11516594

申请日：2006-09-07

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： H03K3/00

CPC分类号： H03K17/04206 ,  H03K17/165 ,  H03K17/6872 ,  H03K19/00361

摘要： When a first signal is switched from an L level to an H level and a second signal is switched from an H level to an L level, and a first constant current source cannot follow the switching immediately thereafter and has not yet been switched, a first node remains at an H level, so an output node remains at an L level. In such state, a second node having been connected to a third node of an H level before the switching becomes connected to the first node of an H level by the switching. At the same time, the output part of an inverter is switched from an H level to an L level, causing the second node to be switched from an H level to an L level as well via a capacitor. At this time, the potential of the first node is reduced to become equal to the second node, to make a transition to an L level.

摘要翻译： 当第一信号从L电平切换到H电平并且第二信号从H电平切换到L电平时，并且第一恒定电流源不能在其后立即切换并且尚未被切换，所以第一信号 节点保持在H电平，因此输出节点保持在L电平。 在这种状态下，在切换之前已经连接到H电平的第三节点的第二节点通过切换连接到H电平的第一节点。 同时，逆变器的输出部分从H电平切换到L电平，使得第二节点也经由电容器从H电平切换到L电平。 此时，第一节点的电位减小到等于第二节点，以转变到L电平。

公开(公告)号：US5654926A

公开(公告)日：1997-08-05

申请号：US605379

申请日：1996-02-22

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C16/06 ,  G11C17/12 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C17/12 ,  G11C7/1048

摘要： A semiconductor memory device pre-charges the electric potential of a selected bit line up to a predetermined electric potential, and judges the electric potential of the selected bit line on the basis of the predetermined electric potential as a threshold value after the pre-charge. Thereby, a semiconductor memory device capable of being read out at high speed can be realized.

摘要翻译： 半导体存储器件对所选择的位线的电位进行预充电直到预定电位，并且在预充电之后，基于预定电位将所选位线的电位判断为阈值。 由此，能够实现能够高速读出的半导体存储器件。

公开(公告)号：US07432740B2

公开(公告)日：2008-10-07

申请号：US11230531

申请日：2005-09-21

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018521

摘要： In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

摘要翻译： 在电平转换电路中，两个P沟道MOS晶体管形成电流镜电路。 当输入信号从“L”电平上升到“H”电平时，连接到一个P沟道MOS晶体管的漏极的N沟道MOS晶体管导通，以防止漏电流流过两个P沟道MOS 晶体管，这降低了功耗。 此外，当输入信号从“L”电平上升到“H”电平时，连接到另一个P沟道MOS晶体管的漏极的P沟道MOS晶体管导通，以固定其中的一个节点的电位 另一个P沟道MOS晶体管的漏极为“H”电平，从而防止节点的电位变得不稳定。

公开(公告)号：US06996704B2

公开(公告)日：2006-02-07

申请号：US10639582

申请日：2003-08-13

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： G06F11/34

CPC分类号： G06F11/3636 ,  G06F11/348 ,  G06F11/364

摘要： A branching source address in an absolute address representation and a branching destination address in a relative address representation are captured from a CPU so that the branching source address and the branching destination address are output tot he trace bus.

摘要翻译： 从CPU中捕获绝对地址表示中的分支源地址和相对地址表示中的分支目标地址，以便将分支源地址和分支目标地址输出到跟踪总线。

公开(公告)号：US6075941A

公开(公告)日：2000-06-13

申请号：US10538

申请日：1998-01-22

申请人： Sakae Itoh ,  Teruaki Kanzaki ,  Tadayuki Akatsuki ,  Tatsuya Sakai ,  Tsutomu Numata ,  Yasuhiro Nakamura

发明人： Sakae Itoh ,  Teruaki Kanzaki ,  Tadayuki Akatsuki ,  Tatsuya Sakai ,  Tsutomu Numata ,  Yasuhiro Nakamura

IPC分类号： G06F11/28 ,  G06F9/06 ,  G06F11/36 ,  G06F15/78 ,  G06F9/445

CPC分类号： G06F11/3656 ,  G06F11/3636

摘要： A microcomputer contains an electrically erasable flash memory for storing a program under development and a debugging circuit 7 having a dedicated input/output terminal for connection to an external ICE 14, and the debugging circuit 7 has a function of communication with a CPU 1, a function of communication with the ICE 14, a function of tracing the operating condition of the CPU 1, a break function of generating a debug interrupt, a function of writing a program code from the ICE 14 into the flash memory 6 and a function of sending the contents of the flash memory 6 to the ICE 14.

摘要翻译： 微型计算机包括用于存储正在开发的程序的电可擦除闪存，以及具有用于连接到外部ICE 14的专用输入/输出端子的调试电路7，调试电路7具有与CPU 1， 与ICE 14通信的功能，跟踪CPU 1的工作状态，产生调试中断的中断功能，将程序代码从ICE14写入闪速存储器6的功能，以及发送功能 闪存6的内容到ICE 14。

公开(公告)号：US20100109745A1

公开(公告)日：2010-05-06

申请号：US12634608

申请日：2009-12-09

申请人： Teruaki Kanzaki

发明人： Teruaki Kanzaki

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

摘要翻译： 在电平转换电路中，两个P沟道MOS晶体管形成电流镜电路。 当输入信号从“L”电平上升到“H”电平时，连接到一个P沟道MOS晶体管的漏极的N沟道MOS晶体管导通，以防止漏电流流过两个P沟道MOS 晶体管，这降低了功耗。 此外，当输入信号从“L”电平上升到“H”电平时，连接到另一个P沟道MOS晶体管的漏极的P沟道MOS晶体管导通，以固定其中的一个节点的电位 另一个P沟道MOS晶体管的漏极为“H”电平，从而防止节点的电位变得不稳定。