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公开(公告)号：US4110260A
公开(公告)日：1978-08-29
申请号：US725457
申请日：1976-09-22
摘要： The electroconductive composite ceramics composed of an independent phase conglomerates having a particle diameter of at least 20.mu. and a continuous phase connecting mutually the independent phase of conglomerates. Particularly, electroconductive composite ceramics composed of (A) 50-98% by weight of an independent phase of conglomerates having a particle diameter of at least 20 which consists essentially of a phase of insulating or semiconductive ceramics having a high melting point or a mixture thereof and (B) 50-2% by weight of a continuous phase of an electroconductive substance connecting mutually the independent phase of conglomerates. The electroconductive composite ceramics exhibit stable electroconductivity-temperature characteristics at a temperature of 1000.degree. C. or higher and have excellent thermal shock resistance, mechanical strength and chemical resistance.
摘要翻译： 导电复合陶瓷由具有至少20微米的粒径的砾石的独立相组成，连续相连接相互独立的砾岩相。 特别地，导电复合陶瓷由（A）50-98重量％的粒径为至少为20的砾石的独立相组成，其主要由具有高熔点的绝缘或半导体陶瓷相或其混合物组成 和（B）50-2重量％的连续相的连续相连接相互独立相的砾岩。 导电性复合陶瓷在1000℃以上的温度下表现出稳定的导电性特性，具有优异的耐热冲击性，机械强度和耐化学性。
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公开(公告)号：US4098725A
公开(公告)日：1978-07-04
申请号：US634150
申请日：1975-11-21
IPC分类号： C04B35/18 , C04B35/19 , C04B35/195 , C04B35/478 , C04B35/71 , H01B1/14 , H01B3/00 , H01C7/02 , H01C7/04 , H05B3/12 , H01B1/08
CPC分类号： C04B35/478 , C04B35/18 , C04B35/19 , C04B35/195 , C04B35/71 , H01B1/14 , H01B3/004 , H01C7/022 , H01C7/043 , H05B3/12
摘要： Low thermally expansive, electroconductive composite sintered ceramics comprised of a phase of at least one ceramics selected from the group consisting of low thermally expansive ceramics and negatively thermally expansive ceramics, having dispersed thereinto substantially in a continuous state a phase of an electroconductive substance such as a metal.
摘要翻译： 低热膨胀导电复合烧结陶瓷，由选自低热膨胀陶瓷和负热膨胀陶瓷的至少一种陶瓷的相组成，其中分散在基本上连续状态下的导电物质如 金属。
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公开(公告)号：US07800168B2
公开(公告)日：2010-09-21
申请号：US11833401
申请日：2007-08-03
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.
摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。
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公开(公告)号：US07319257B2
公开(公告)日：2008-01-15
申请号：US11626141
申请日：2007-01-23
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US20070114570A1
公开(公告)日：2007-05-24
申请号：US11626141
申请日：2007-01-23
IPC分类号： H01L31/00
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US20060113613A1
公开(公告)日：2006-06-01
申请号：US11331160
申请日：2006-01-13
申请人： Hideaki Ninomiya , Tomoki Inoue
发明人： Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L29/76
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
摘要翻译： 本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接 区域和止挡区域。
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公开(公告)号：US20050189137A1
公开(公告)日：2005-09-01
申请号：US11059585
申请日：2005-02-17
IPC分类号： C04B35/622 , C04B35/00 , C04B35/495 , H01G4/06 , H01G4/20 , H05K1/03 , H05K1/09 , H05K1/16 , H05K3/00 , H05K3/46
CPC分类号： H05K1/162 , H05K1/0306 , H05K3/005 , H05K3/4611 , H05K3/4629 , H05K2201/0187 , Y10T29/49155 , Y10T29/49162 , Y10T29/49163 , Y10T29/49165 , Y10T156/1056 , Y10T156/1057 , Y10T428/24322
摘要： An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.
摘要翻译： 本发明的目的是在多层陶瓷基板中的片材的主表面的方向上彼此电连接不同的电介质，并且增加设计的柔性程度，并使多层陶瓷基板的尺寸更小。 根据本发明的多层陶瓷基板由多个层叠陶瓷基板形成，该多个层叠陶瓷基板包括这样的不同材料的复合陶瓷基板，该复合陶瓷基板是通过将第二陶瓷基板插入在第一陶瓷基板中形成的突出部分而形成的， 平面化其顶表面和底表面，其中导电层形成在穿过不同材料的复合陶瓷衬底的界面的第一陶瓷衬底和第二陶瓷衬底之间的边界的部分中。
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公开(公告)号：US20050161768A1
公开(公告)日：2005-07-28
申请号：US11016810
申请日：2004-12-21
IPC分类号： H01L29/78 , H01L27/04 , H01L27/088 , H01L29/423 , H01L29/739 , H01L31/113
CPC分类号： H01L29/7397 , H01L29/4232 , H01L29/42372 , H01L29/7395
摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.
摘要翻译： 半导体器件包括具有第一表面和第二表面的第一导电类型的第一基底层; 形成在第一表面上的第二导电类型的第二基层; 通过经由栅极绝缘膜将导电材料嵌入多个沟槽而形成的第一和第二栅电极，所述多个沟槽形成为使得沟槽的底部到达第一基底层; 源极层，其形成在第二基极层的表面区域上，以与设置有第一栅电极的沟槽的两个侧壁相邻，并且设置有第二栅电极的沟槽的一个侧壁 ， 分别; 形成在第二表面上的第二导电类型的发射极层; 在第二基极层和源极层上形成的发射极; 在发射极层上形成的集电极; 以及分别电连接到第一和第二栅电极的第一和第二端子。
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公开(公告)号：US20050056912A1
公开(公告)日：2005-03-17
申请号：US10689608
申请日：2003-10-22
申请人： Hideaki Ninomiya , Tomoki Inoue
发明人： Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/06 , H01L29/40 , H01L29/41 , H01L29/861 , H01L29/76
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
摘要翻译： 本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接 区域和止挡区域。
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公开(公告)号：US5523729A
公开(公告)日：1996-06-04
申请号：US190321
申请日：1993-11-19
申请人： Shinya Nakai , Hideaki Ninomiya , Hideaki Shimoda
发明人： Shinya Nakai , Hideaki Ninomiya , Hideaki Shimoda
CPC分类号： H01P1/20345 , H01P1/2056 , H03H7/09 , H03H7/1708 , H03H7/1775 , H03H2001/0085
摘要： A multilayer band pass filter includes a zero point forming capacitor formed by a plurality of capacitors connected in series between first and second extension electrodes, and intermediate capacitors connected between each pair of adjacent series capacitors and the open end of a core conductor. Therefore, zero points can be formed at the lower and upper limits of a given band. The capacity of these capacitors is adjustable via extension electrodes which extend outside the baked ceramic casing, thereby allowing adjustment to be made to the zero point.
摘要翻译： 多层带通滤波器包括由串联连接在第一和第二延伸电极之间的多个电容器和连接在每对相邻串联电容器和芯导体的开口端之间的中间电容器形成的零点形成电容器。 因此，可以在给定频带的下限和上限处形成零点。 这些电容器的容量可以通过延伸电极调节，延伸电极延伸到烘烤的陶瓷外壳的外部，从而允许调整到零点。
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