公开(公告)号：US06909624B2

公开(公告)日：2005-06-21

申请号：US10624890

申请日：2003-07-23

申请人： Hiroyuki Sadakata ,  Naoki Kuroda

发明人： Hiroyuki Sadakata ,  Naoki Kuroda

IPC分类号： G01R31/28 ,  G11C29/26 ,  G11C29/34 ,  G11C5/06

CPC分类号： G11C29/56004 ,  G11C29/26 ,  G11C2029/0401 ,  G11C2029/1806 ,  G11C2029/2602

摘要： In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested using the same test pattern (for example, HALF-MARCH) even if a special pin is provided for each RAM, because X, Y address mapping differs between the different RAMs; accordingly, the test has to be performed by dividing the RAMs into groups each consisting of RAMs having the same memory space, and this has lead to increased test time. An external address signal and a test-only address signal are provided as RAM control signals and, in the latter case, the number of X, Y addresses in each of the RAMs 4 and 5 is set equal to that of the largest capacity RAM 3 within the same chip, thereby making the X, Y address mapping the same for all the RAMs 3 to 5.

摘要翻译： 在近来的系统LSI中，根据系统侧的需要，将单个芯片上的容量和位宽不同的多个RAM进行安装。 然而，当测试多个RAM时，如果RAM的容量不同，即使为每个RAM提供特殊引脚，也不能使用相同的测试模式（例如，HALF-MARCH）进行测试，因为X，Y地址映射 不同的RAM之间有所不同; 因此，必须通过将RAM分成由具有相同存储空间的RAM组成的组来执行测试，并且这导致增加的测试时间。 提供外部地址信号和仅测试地址信号作为RAM控制信号，并且在后一种情况下，每个RAM4和5中的X，Y地址的数量被设置为等于最大容量RAM 3的数量 在同一个芯片内，从而使X，Y地址映射对于所有RAM3至5都是相同的。

公开(公告)号：US06788565B2

公开(公告)日：2004-09-07

申请号：US10394262

申请日：2003-03-24

申请人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

发明人： Masashi Agata ,  Kazunari Takahashi ,  Masanori Shirahama ,  Naoki Kuroda ,  Hiroyuki Sadakata ,  Ryuji Nishihara

IPC分类号： G11C1140

CPC分类号： G11C11/405 ,  H01L27/108

摘要： A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有第一晶体管，第二晶体管具有连接到第一晶体管的源极或漏极的一部分的源极或漏极;以及第三晶体管，源极或漏极连接到第一晶体管， 第一晶体管的源极或漏极的另一部分。 第一晶体管在其通道中累积从第二和第三晶体管传送的电荷。

公开(公告)号：US07561080B2

公开(公告)日：2009-07-14

申请号：US11790737

申请日：2007-04-27

申请人： Naoki Yamada ,  Naoki Kuroda

发明人： Naoki Yamada ,  Naoki Kuroda

IPC分类号： H03M9/00

CPC分类号： H03M1/1071

摘要： The semiconductor integrated circuit includes: a plurality of macro cells; and a serial-parallel conversion circuit for converting a serial signal inputted from outside to generate parallel selection control signals during testing, or an A/D conversion circuit for converting an analog signal inputted from outside to generate digital selection control signals during testing. One or more among, the plurality of macro cells are selected based on the selection control signals and brought to a test operation state.

摘要翻译： 半导体集成电路包括：多个宏小区; 以及用于转换从外部输入的串行信号以在测试期间产生并行选择控制信号的串并转换电路，或用于转换从外部输入的模拟信号以在测试期间产生数字选择控制信号的A / D转换电路。 基于选择控制信号选择多个宏小区中的一个或多个，并进入测试操作状态。

公开(公告)号：US07349267B2

公开(公告)日：2008-03-25

申请号：US11492176

申请日：2006-07-25

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C17/10

摘要： In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. In an active period, the source bias control circuits perform potential control so that one or more of the source lines selected by row predecoders which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

摘要翻译： 在存储单元阵列中，提供源极线，使得每个源极线连接到属于相邻两行的存储单元中的每一个，以及用于提供高于地的源极偏置电位的多个源极偏置控制电路 提供电位并且低于电源电位以分别对应于源极线。 在有源时段中，源极偏置控制电路进行电位控制，使得由行预解码器选择的一个或多个未连接到要读出的存储单元之一的源极线被控制为处于 提供源极偏置电位。

公开(公告)号：US07254072B2

公开(公告)日：2007-08-07

申请号：US11074722

申请日：2005-03-09

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C2207/002

摘要： A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

摘要翻译： 提供一种半导体存储器件，其包括对应于全局数据线对的预充电电路，而不是与本地数据线对对应的预充电电路。 在命令等待状态下，数据线选择开关被控制为处于连接状态，使得本地数据线对和全局数据线对在彼此连接的同时被预先充电。 在命令执行状态下，命令执行不需要的数据线选择开关之一处于打开状态。 类似地，可以提供仅包括对应于本地数据线对的预充电电路的半导体存储器件。

公开(公告)号：US4448099A

公开(公告)日：1984-05-15

申请号：US328380

申请日：1981-12-07

申请人： Naoki Kuroda ,  Kimihiro Tsuge

发明人： Naoki Kuroda ,  Kimihiro Tsuge

IPC分类号： B23D33/00 ,  B21D43/28 ,  B26D5/20

CPC分类号： B21D43/282 ,  Y10T83/0448 ,  Y10T83/0467 ,  Y10T83/2183 ,  Y10T83/4453 ,  Y10T83/4632

摘要： An improved method of operating an apparatus to cut sheet material workpieces eliminates the inadvertent dropping of a relatively small scrap or remainder portion of a workpiece into a clearance space between a pair of cutter blades and a discharge conveyor. Thus, a relatively large sheet metal workpiece is gripped by a holder which moves the workpiece relative to a pair of blades. The blades are moved relative to each other to cut the workpiece to form a product having a desired configuration. The product is dropped onto a discharge conveyor. In order to prevent a relatively small scrap piece remaining in the holder from being dropped into a space between the discharge conveyor and the blades, the holder is extended through the space between the blades to a location over the discharge conveyor and is opened to drop the scrap or remainder portion of the workpiece onto the discharge conveyor.

摘要翻译： 操作切割片材工件的设备的改进方法消除了相对较小的废料或剩余部分的意外掉落到一对切割刀片和排出输送机之间的间隙空间中。 因此，相对较大的钣金工件被保持件夹持，所述保持件相对于一对刀片移动工件。 刀片相对于彼此移动以切割工件以形成具有期望构造的产品。 产品落在排放输送机上。 为了防止保持器中残留的相对较小的碎屑落入排出传送器和叶片之间的空间中，保持器通过叶片之间的空间延伸到排出输送器上方的位置，并且打开以使 废料或剩余部分的工件放在排放输送机上。

公开(公告)号：US4297927A

公开(公告)日：1981-11-03

申请号：US127800

申请日：1980-03-06

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： B23Q3/06 ,  B21D43/00 ,  B21D43/10 ,  B21D43/28 ,  B23D33/10 ,  B26D7/01

CPC分类号： B21D43/003 ,  B21D43/10 ,  B21D43/287 ,  Y10T83/04 ,  Y10T83/051 ,  Y10T83/4632 ,  Y10T83/4637 ,  Y10T83/6563

摘要： A sheet metal workpiece is held by holders as the workpiece is cut and moved relative to a device such as a shearing machine or punch press. An improved apparatus and method is provided to precisely position the sheet metal workpiece relative to the holders. This apparatus includes a first gripper assembly which is disposed at an opening in a support structure for the sheet metal workpiece. The first gripper assembly moves the workpiece to position it along a first axis. A second gripper assembly is disposed at another opening in the support structure and moves the workpiece to position it along a second axis which extends transversely to the first axis. The two gripper assemblies can be moved between extended positions projecting upwardly from the support structure and retracted positions in which the gripper assemblies are disposed within the support structure.

摘要翻译： 当工件被切割并相对于诸如剪切机或冲压机的装置移动时，钣金工件被保持器保持。 提供了一种改进的装置和方法来精确地定位钣金工件相对于支架。 该装置包括第一夹持器组件，该第一夹持器组件设置在用于金属板工件的支撑结构中的开口处。 第一夹具组件移动工件以使其沿着第一轴定位。 第二夹持器组件设置在支撑结构中的另一开口处，并且移动工件以使其沿着横向于第一轴线延伸的第二轴定位。 两个夹持器组件可以在从支撑结构向上突出的延伸位置和在夹持器组件设置在支撑结构内的缩回位置之间移动。

公开(公告)号：US20100178879A1

公开(公告)日：2010-07-15

申请号：US12730310

申请日：2010-03-24

申请人： Yusuke Sato ,  Nobuyoshi Maejima ,  Tomoaki Kudaishi ,  Shinji Moriyama ,  Naoki Kuroda ,  Ryota Sato ,  Masashi Okano

发明人： Yusuke Sato ,  Nobuyoshi Maejima ,  Tomoaki Kudaishi ,  Shinji Moriyama ,  Naoki Kuroda ,  Ryota Sato ,  Masashi Okano

IPC分类号： H04B1/04

CPC分类号： H03F3/195 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

摘要翻译： 提供了一种技术，用于在增强电子设备的性能的同时，实现具有功率放大器电路的电子设备的尺寸的减小。 用于移动通信设备的RF功率模块包括安装在布线板上的第一和第二半导体芯片，无源部件以及第一和第二集成无源部件。 在第一半导体芯片中，形成用于GSM 900和DCS 1800的功率放大器电路的MISFET元件，并且还形成控制电路。 在第一集成无源部件中，形成用于GSM 900的低通滤波器电路，并且在第二集成无源部件中形成用于DCS 1800的低通滤波器电路。 在第二半导体芯片中，形成用于GSM 900和DCS 1800的天线切换电路。 在布线板的上表面上，第二半导体芯片设置在集成的无源元件之间的第一半导体芯片的旁边。

公开(公告)号：US07656732B2

公开(公告)日：2010-02-02

申请号：US12191011

申请日：2008-08-13

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C7/02

CPC分类号： G11C11/4099 ,  G11C7/08 ,  G11C7/14 ,  G11C7/227

摘要： In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.

摘要翻译： 在其中动态数据在位线上被放大和读取的诸如动态随机存取存储器（DRAM）的半导体存储装置中，连接到存储器阵列的数据线的数据线读出放大器/写入缓冲器和数据 提供连接到虚拟存储器阵列的虚拟数据线的线读出放大器控制信号产生逻辑电路。 读出放大器根据逻辑电路的输出信号而被激活。

公开(公告)号：US07417911B2

公开(公告)日：2008-08-26

申请号：US11484756

申请日：2006-07-12

申请人： Naoki Kuroda

发明人： Naoki Kuroda

IPC分类号： G11C7/00

CPC分类号： G11C7/1048 ,  G11C2207/002

摘要： A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

摘要翻译： 提供一种半导体存储器件，其包括对应于全局数据线对的预充电电路，而不是与本地数据线对对应的预充电电路。 在命令等待状态下，数据线选择开关被控制为处于连接状态，使得本地数据线对和全局数据线对在彼此连接的同时被预先充电。 在命令执行状态下，命令执行不需要的数据线选择开关之一处于打开状态。 类似地，可以提供仅包括对应于本地数据线对的预充电电路的半导体存储器件。