公开(公告)号：US06292040B1

公开(公告)日：2001-09-18

申请号：US09047375

申请日：1998-03-25

申请人： Hisashi Iwamoto ,  Wataru Sakamoto ,  Naoya Watanabe

发明人： Hisashi Iwamoto ,  Wataru Sakamoto ,  Naoya Watanabe

IPC分类号： H03L706

CPC分类号： H03L7/07 ,  H03K23/544 ,  H03L7/0814 ,  H03L7/089 ,  Y10S331/02

摘要： An internal clock signal generating circuit includes a selector, a delay line, a 2-frequency divider, a phase comparator and a shift register. The selector alternately selects an external clock signal and an internal clock signal output from the delay line and outputs the selected signal to the delay line. The delay line receiving the signal delays the external clock signal, and delays the internal clock signal output from itself. The 2-frequency divider divides frequency of the internal clock signal by 2. Phase comparator compares phases of the external clock signal and the output signal from the 2-frequency divider. Delay time of the delay line is adjusted by the phase comparator and the shift register so that the phase difference is made 0.

摘要翻译： 内部时钟信号发生电路包括选择器，延迟线，2分频器，相位比较器和移位寄存器。 选择器交替地选择从延迟线输出的外部时钟信号和内部时钟信号，并将选择的信号输出到延迟线。 接收信号的延迟线延迟外部时钟信号，并延迟其自身输出的内部时钟信号。 2分频器将内部时钟信号的频率除以2.相位比较器比较外部时钟信号和2分频器的输出信号的相位。 延迟线的延迟时间由相位比较器和移位寄存器调整，使得相位差为0。

公开(公告)号：US5940344A

公开(公告)日：1999-08-17

申请号：US53058

申请日：1998-04-01

申请人： Yasumitsu Murai ,  Wataru Sakamoto ,  Hisashi Iwamoto

发明人： Yasumitsu Murai ,  Wataru Sakamoto ,  Hisashi Iwamoto

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/00

CPC分类号： G11C7/22

摘要： In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.

摘要翻译： 在内部时钟信号发生电路中，用于检测外部时钟信号和内部时钟信号之间的相位差的相位比较器包括相对于信号线的晶体管和电容器，通过该信号线发送对应于外部时钟信号的时钟信号 以及相对于信号线的晶体管和电容器，通过该晶体管和电容器发送与内部时钟信号对应的时钟信号。 具有两个信号线的信号的滞后相位的信号的上升定时变得更加平缓。 结果，相位差增大，相位比较器可以高精度地比较相位。

公开(公告)号：US06184738B2

公开(公告)日：2001-02-06

申请号：US09019199

申请日：1998-02-05

申请人： Hisashi Iwamoto ,  Aiko Nishino ,  Wataru Sakamoto

发明人： Hisashi Iwamoto ,  Aiko Nishino ,  Wataru Sakamoto

IPC分类号： H03L500

CPC分类号： H03K19/018528

摘要： An input buffer of a semiconductor device is provided. A first voltage shift circuit converts an input signal formed of a low amplitude logic signal overlapping 1.65V or 2.9V to a first signal formed of a complimentary signal formed of the low amplitude logic signal overlapping 2.9V or 1.65V. A second voltage shift circuit converts a reference potential of 1.65V or 2.9V to a second signal of 2.9V or 1.65V. A differential amplifier compares the reference potential with the input signal when the reference potential is 1.65V, and compares the first signal and the second signal when the reference potential is 2.9V. The input buffer thus operates normally whichever of 1.65V and 2.9V is the reference potential.

摘要翻译： 提供半导体器件的输入缓冲器。第一电压移位电路将由1.65V或2.9V重叠的低幅度逻辑信号形成的输入信号转换成由与低幅度逻辑信号形成的互补信号形成的第一信号重叠2.9 V或1.65V。 第二电压移位电路将1.65V或2.9V的参考电位转换为2.9V或1.65V的第二信号。 当参考电位为1.65V时，差分放大器将参考电位与输入信号进行比较，当参考电位为2.9V时，比较第一信号和第二信号。 因此，输入缓冲器通常正常为1.65V和2.9V为参考电位。

公开(公告)号：US5940328A

公开(公告)日：1999-08-17

申请号：US917211

申请日：1997-08-25

申请人： Hisashi Iwamoto ,  Wataru Sakamoto

发明人： Hisashi Iwamoto ,  Wataru Sakamoto

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C16/04

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： One strobe signal (QS) is outputted from a group of two adjacent memory chips (MC(i-1), MCi) in each module. In each group, the second memory chip (MCi) receives a data mask signal (DQM(i-1)) inputted to the adjacent first memory chip (MC(i-1)) as a data mask control signal (DQMCi), and stops outputting the strobe signal (QS) when both the data mask signal (DQMi) for the second memory chip (MCi) and the data mask control signal (DQMCi) are activated. Each memory chip (MCi) receives the data mask signal (DQMi) and stops outputting data. In a synchronous DRAM using a strobe signal as a trigger, this configuration allows reduction in the number of strobe signals.

摘要翻译： 在每个模块中从一组两个相邻的存储器芯片（MC（i-1），MCi）输出一个选通信号（QS）。 在每组中，第二存储器芯片（MCi）接收输入到相邻的第一存储器芯片（MC（i-1））的数据掩码信号（DQM（i-1））作为数据掩码控制信号（DQMCi），以及 当第二存储器芯片（MCi）的数据掩码信号（DQMi）和数据掩码控制信号（DQMCi）都被激活时，停止输出选通信号（QS）。 每个存储器芯片（MCi）接收数据屏蔽信号（DQMi）并停止输出数据。 在使用选通信号作为触发的同步DRAM中，该配置允许减少选通信号的数量。

公开(公告)号：US5404338A

公开(公告)日：1995-04-04

申请号：US189247

申请日：1994-01-31

申请人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

发明人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

IPC分类号： G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  F02B2075/027

摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

摘要翻译： 在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。 提供了两个小型存储器阵列的本地I / O线对（LIO）。 跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。 连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。 激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。 从而，可以同时读取多个比特，而不增加互连占用的面积。 使用读出放大器激活信号进行连接开关的控制。 数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。 外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。

公开(公告)号：US5517462A

公开(公告)日：1996-05-14

申请号：US381586

申请日：1995-01-31

申请人： Hisashi Iwamoto ,  Yasumitsu Murai ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

发明人： Hisashi Iwamoto ,  Yasumitsu Murai ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

IPC分类号： G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  F02B2075/027

摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

公开(公告)号：US06333873B1

公开(公告)日：2001-12-25

申请号：US08942692

申请日：1997-09-29

申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Kouji Hayano

发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Kouji Hayano

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C5/146 ,  G11C11/005

摘要： A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

摘要翻译： 半导体存储器件接收独立于对存储器件的访问而重复产生的外部控制信号。 存储器件包括用于响应于控制信号产生期望的内部电压的内部电压发生器。 内部电压发生器包括响应于控制信号的电荷泵电路。 内部电压可以提供诸如衬底偏置电压的负电压，或者可以是在工作电源电压上升压的正电压并且用作升压的字线驱动信号。 该方案消除了用于向电荷泵电路产生重复时钟信号的振荡器，导致半导体存储器件的电流消耗降低和芯片面积减小。

公开(公告)号：US6151273A

公开(公告)日：2000-11-21

申请号：US362667

申请日：1999-07-29

申请人： Hisashi Iwamoto ,  Takeshi Kajimoto

发明人： Hisashi Iwamoto ,  Takeshi Kajimoto

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/18 ,  G11C2207/229

摘要： A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

摘要翻译： 提供了能够提高实质的传输速率的同步半导体存储器件。 响应于紧跟在动作命令之后的写入命令，控制信号产生电路将无效使能信号应用于读取的前置放大器和写入缓冲器。 响应于写入命令和预充电命令，控制信号产生电路产生有效使能信号，读取的前置放大器和写入缓冲器将存储在FIFO中的数据写入存储单元。 由于在接收到动作命令之后的写入命令时不执行后期写入，因此可以防止数据向不想要的地址的错误写入。

公开(公告)号：US6118730A

公开(公告)日：2000-09-12

申请号：US295361

申请日：1999-04-21

申请人： Takashi Kubo ,  Yasumitsu Murai ,  Hisashi Iwamoto

发明人： Takashi Kubo ,  Yasumitsu Murai ,  Hisashi Iwamoto

IPC分类号： G11C11/407 ,  G11C7/22 ,  H03D13/00 ,  H03K5/26 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  G11C8/00

CPC分类号： H03L7/089 ,  G11C7/22 ,  H03D13/004 ,  H03K5/26 ,  H03L7/0814

摘要： The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.

摘要翻译： 相位比较器接收接收第一输入信号的缓冲器的输出和接收第二输入信号的缓冲器的输出，并且作为相位比较的结果输出信号SLOW，FAST。 相位比较器包括用于放大两个输入信号之间的相位差的波形处理电路和用于通过波形处理电路放大的相位差进行相位比较的比较电路，并输出信号SLOW，FAST。 由于波形处理电路的功能，可以显着提高相位比较器的性能，而不必大幅提高比较电路的性能。

公开(公告)号：US5844859A

公开(公告)日：1998-12-01

申请号：US923689

申请日：1997-09-04

申请人： Hisashi Iwamoto ,  Yasuhiro Konishi

发明人： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.

摘要翻译： 当操作频率增加并且CAS延迟设置得更长时，响应于CAS延迟的改变，数据写入结束时间被延迟特定时间。 具体时间大于对应于CAS延迟的周期。 具体时间可以是写入第二位数据所需的最短时间。 也可以通过将外部时钟信号的一个时钟周期延迟存储器本身内部的写入定时（激活和去激活）来扩大写入裕度。 因此，即使操作频率增加，也可以在SDRAM中确保第二位数据的写周期。