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1.发明授权Synchronous type semiconductor memory device operating in synchronization with an external clock signal 失效与外部时钟信号同步工作的同步型半导体存储器件
公开(公告)号：US5404338A
公开(公告)日：1995-04-04
申请号：US189247
申请日：1994-01-31
IPC分类号： G11C11/407 , F02B75/02 , G11C7/10 , G11C11/401 , G11C11/409 , G11C13/00
CPC分类号： G11C7/222 , G11C7/1072 , F02B2075/027
摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.
摘要翻译： 在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。 提供了两个小型存储器阵列的本地I / O线对（LIO）。 跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。 连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。 激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。 从而，可以同时读取多个比特，而不增加互连占用的面积。 使用读出放大器激活信号进行连接开关的控制。 数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。 外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。
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公开(公告)号：US5517462A
公开(公告)日：1996-05-14
申请号：US381586
申请日：1995-01-31
IPC分类号： G11C11/407 , F02B75/02 , G11C7/10 , G11C11/401 , G11C11/409 , G11C13/00
CPC分类号： G11C7/222 , G11C7/1072 , F02B2075/027
摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.
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公开(公告)号：US5815462A
公开(公告)日：1998-09-29
申请号：US800905
申请日：1997-02-12
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/409 , G11C8/00
CPC分类号： G11C7/225 , G11C7/1039 , G11C7/1072 , G11C7/22
摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
摘要翻译： 用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。 可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。 内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过 输出缓冲区。 提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。
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公开(公告)号：US5592434A
公开(公告)日：1997-01-07
申请号：US548285
申请日：1995-10-25
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1048 , G11C7/1072
摘要： To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.
摘要翻译： 对于一个存储器阵列，两个系统中的全局信号输入/输出线对，用于以时钟周期交替地将全局IO线对连接到写缓冲器组的开关，以及用于将全局IO线对连接到等于 提供了基于时钟周期的交替电路。 在一个时钟周期内，可以并行执行通过一个全局IO线对写入数据和对另一个全局IO线对进行均衡。 因此，可以高频地容易地写入数据。
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5.发明授权Phase comparator with improved comparison precision and synchronous semiconductor memory device employing the same 失效具有改进比较精度的相位比较器和采用该比较精度的同步半导体存储器件
公开(公告)号：US6118730A
公开(公告)日：2000-09-12
申请号：US295361
申请日：1999-04-21
申请人： Takashi Kubo , Yasumitsu Murai , Hisashi Iwamoto
发明人： Takashi Kubo , Yasumitsu Murai , Hisashi Iwamoto
CPC分类号： H03L7/089 , G11C7/22 , H03D13/004 , H03K5/26 , H03L7/0814
摘要： The phase comparator receives an output of a buffer receiving the first input signal and an output of a buffer receiving the second input signal, and outputs signals SLOW, FAST as a result of phase comparison. The phase comparator includes a waveform processing circuit for enlarging the phase difference between two input signals, and a comparison circuit for performing phase comparison based on the phase difference enlarged by the waveform processing circuit and outputting signals SLOW, FAST. Because of the function of the waveform processing circuit, the performance of the phase comparator can be improved significantly, without having to largely improve the performance of the comparison circuit.
摘要翻译： 相位比较器接收接收第一输入信号的缓冲器的输出和接收第二输入信号的缓冲器的输出，并且作为相位比较的结果输出信号SLOW，FAST。 相位比较器包括用于放大两个输入信号之间的相位差的波形处理电路和用于通过波形处理电路放大的相位差进行相位比较的比较电路，并输出信号SLOW，FAST。 由于波形处理电路的功能，可以显着提高相位比较器的性能，而不必大幅提高比较电路的性能。
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6.发明授权
公开(公告)号：US5940344A
公开(公告)日：1999-08-17
申请号：US53058
申请日：1998-04-01
IPC分类号： G11C11/407 , G11C7/22 , G11C8/00
CPC分类号： G11C7/22
摘要： In an internal clock signal generation circuit, a phase comparator for detecting phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the external clock signal is transmitted, and a transistor and a capacitor with respect to a signal line through which a clock signal corresponding to the internal clock signal is transmitted. The rising timing of the signal having a more lagging phase of the signals of the two signal lines becomes more gentle. As a result, the phase difference is increased, and the phase comparator can compare the phase at high precision.
摘要翻译： 在内部时钟信号发生电路中，用于检测外部时钟信号和内部时钟信号之间的相位差的相位比较器包括相对于信号线的晶体管和电容器，通过该信号线发送对应于外部时钟信号的时钟信号 以及相对于信号线的晶体管和电容器，通过该晶体管和电容器发送与内部时钟信号对应的时钟信号。 具有两个信号线的信号的滞后相位的信号的上升定时变得更加平缓。 结果，相位差增大，相位比较器可以高精度地比较相位。
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7.发明授权Internal clock signal generation circuit including delay line, and synchronous type semiconductor memory device including internal clock signal 失效内部时钟信号发生电路包括延迟线，同步型半导体存储器件包括内部时钟信号
公开(公告)号：US5946268A
公开(公告)日：1999-08-31
申请号：US012558
申请日：1998-01-23
申请人： Hisashi Iwamoto , Yasumitsu Murai
发明人： Hisashi Iwamoto , Yasumitsu Murai
IPC分类号： G11C11/407 , G06F1/06 , G11C7/22 , G11C11/4076 , H03K5/00 , H03K5/13 , H03L7/00 , G11C7/00
CPC分类号： G11C7/22 , H03K5/133 , H03K2005/00071
摘要： An internal clock generation circuit includes a delay line in which a plurality of inverter circuits are connected in series. A switch and a capacitor are connected to an output node of each inverter circuit. The switch connected to each inverter circuit is turned on/off individually according to respective control signals. In response to the switch being turned on, the output node of a corresponding inverter circuit and the capacitor are connected, whereby the capacitance of the output node of the corresponding inverter circuit is altered. As a result, the transmission rate of the signal is altered.
摘要翻译： 内部时钟生成电路包括多个逆变器电路串联连接的延迟线。 开关和电容器连接到每个逆变器电路的输出节点。 连接到每个逆变器电路的开关根据相应的控制信号单独打开/关闭。 响应于开关导通，相应的逆变器电路的输出节点和电容器被连接，从而相应的逆变器电路的输出节点的电容被改变。 结果，信号的传输速率被改变。
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公开(公告)号：US08508986B2
公开(公告)日：2013-08-13
申请号：US13188924
申请日：2011-07-22
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.
摘要翻译： 一种具有第一和第二数字线驱动器和位线驱动器的半导体器件。 当从外部输入一个段的地址时，段解码器选择与地址相对应的一个段，并将其与所选择的第一位数字线驱动器相连。 当从外部输入两个或更多个段的地址时，段解码器选择对应于地址的两个或多个段，并将所选择的两个或多个段耦合到相应的数字线路驱动器。
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公开(公告)号：US07872907B2
公开(公告)日：2011-01-18
申请号：US12340513
申请日：2008-12-19
申请人： Shota Okayama , Yasumitsu Murai
发明人： Shota Okayama , Yasumitsu Murai
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C5/025 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0023 , G11C13/0028
摘要： There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.
摘要翻译： 提供了能够进行高速数据读取并减小用于激活字线的驱动电路的面积的半导体器件。 通过通过具有低电阻并且在多个点处耦合到字线的公共字线的信号传输，可以高速读取数据。 此外，由于公共字线被提供为多个存储块的公共信号，所以字线驱动器可以被提供给存储器块公用。 此外，通过配置与子数字对应的锁存电路来保持公共字线的有效状态，可以通过公共字线在数据写入期间发送行选择信号，从而减少金属布线 层。
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公开(公告)号：US20090168502A1
公开(公告)日：2009-07-02
申请号：US12340513
申请日：2008-12-19
申请人： Shota Okayama , Yasumitsu Murai
发明人： Shota Okayama , Yasumitsu Murai
CPC分类号： H01L27/228 , G11C5/025 , G11C11/1653 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C13/0023 , G11C13/0028
摘要： There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.
摘要翻译： 提供了能够进行高速数据读取并减小用于激活字线的驱动电路的面积的半导体器件。 通过通过具有低电阻并且在多个点处耦合到字线的公共字线的信号传输，可以高速读取数据。 此外，由于公共字线被提供为多个存储块的公共信号，所以字线驱动器可以被提供给存储器块公用。 此外，通过配置与子数字对应的锁存电路来保持公共字线的有效状态，可以通过公共字线在数据写入期间发送行选择信号，从而减少金属布线 层。
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