公开(公告)号：US5404338A

公开(公告)日：1995-04-04

申请号：US189247

申请日：1994-01-31

申请人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

发明人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

IPC分类号： G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  F02B2075/027

摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

摘要翻译： 在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。 提供了两个小型存储器阵列的本地I / O线对（LIO）。 跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。 连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。 激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。 从而，可以同时读取多个比特，而不增加互连占用的面积。 使用读出放大器激活信号进行连接开关的控制。 数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。 外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。

公开(公告)号：US5517462A

公开(公告)日：1996-05-14

申请号：US381586

申请日：1995-01-31

申请人： Hisashi Iwamoto ,  Yasumitsu Murai ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

发明人： Hisashi Iwamoto ,  Yasumitsu Murai ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

IPC分类号： G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  F02B2075/027

摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

公开(公告)号：US5815462A

公开(公告)日：1998-09-29

申请号：US800905

申请日：1997-02-12

申请人： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

发明人： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/225 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/22

摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

摘要翻译： 用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。 可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。 内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过 输出缓冲区。 提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

公开(公告)号：US5587950A

公开(公告)日：1996-12-24

申请号：US461907

申请日：1995-06-05

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/40 ,  G11C7/00

CPC分类号： G11C29/40 ,  G11C29/26

摘要： In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

公开(公告)号：US5471430A

公开(公告)日：1995-11-28

申请号：US245784

申请日：1994-05-19

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/02 ,  G11C29/08 ,  G11C11/34

CPC分类号： G11C29/02 ,  G11C11/406

摘要： A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.

摘要翻译： 同步半导体存储器件包括自动刷新检测电路，用于检测根据自动刷新命令指定自动刷新模式，用于产生刷新地址的地址计数器，用于根据存储器阵列刷新存储器阵列的刷新执行单元 自动刷新检测信号和刷新地址，用于根据自动刷新检测信号在经过规定时间之后使刷新执行单元失活的灭活电路，用于使灭活电路处于不可操作状态的计数器检查模式检测电路 根据计数器检查模式命令，以及第二失活电路，用于根据预充电命令产生的预充电检测信号，使刷新执行单元失效。 因此，提供了具有可以测试内部刷新地址计数器的功能的操作模式的同步半导体存储器件。

公开(公告)号：US6157992A

公开(公告)日：2000-12-05

申请号：US768089

申请日：1996-12-16

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/407 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G06F12/00

CPC分类号： G11C7/1072

摘要： A read enable signal OEMF activated in response to an input command is applied to an N minus 2 clock shift circuit included in an output control circuit for implementation of ZCAS latency. An output signal of the N minus 2 clock shift circuit and an internal mask instructing signal activated in response to an external mask instructing signal are logically processed and applied to a one-clock shift circuit. According to an output signal OEMQM of one-clock shift circuit, a data output enable signal OEM controlling activation/inactivation of an output buffer circuit is activated/inactivated. Data output controlling portion occupying area of a synchronous dynamic random access memory is reduced and timings of activation/inactivation of data output by different commands are made the same.

摘要翻译： 响应于输入命令而激活的读使能信号OEMF被施加到包括在用于实现ZCAS延迟的输出控制电路中的N-2时钟移位电路。 N减2时钟移位电路的输出信号和响应于外部掩码指示信号而被激活的内部掩码指示信号被逻辑地处理并施加到一个时钟的移位电路。 根据一时钟移位电路的输出信号OEMQM，激活/禁止输出缓冲电路的数据输出使能信号OEM控制激活/失活。 同步动态随机存取存储器的数据输出控制部占用面积减少，不同命令输出的数据的激活/失活定时相同。

公开(公告)号：US5818768A

公开(公告)日：1998-10-06

申请号：US767496

申请日：1996-12-16

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1045

摘要： A correspondence defining circuit changes a correspondence between an external signal and an internal signal and supplies it to a mode designating signal generating circuit according to a logic state of an operation mode switching signal. The mode designating signal generating circuit activates a mode designating signal which designates a specific operation mode in a semiconductor device when the internal signal satisfies a prescribed condition. An operation mode setting circuit, applicable to applications in which states of external signals are different without a change of its internal structure, is thus provided.

摘要翻译： 对应定义电路改变外部信号和内部信号之间的对应关系，并根据操作模式切换信号的逻辑状态将其提供给模式指定信号发生电路。 当内部信号满足规定条件时，模式指定信号发生电路激活指定半导体器件中的特定操作模式的模式指定信号。 因此，提供了适用于其外部信号的状态不同而不改变其内部结构的应用的操作模式设定电路。

公开(公告)号：US5511029A

公开(公告)日：1996-04-23

申请号：US246582

申请日：1994-05-19

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/40 ,  G11C7/00

CPC分类号： G11C29/40 ,  G11C29/26

摘要： In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

摘要翻译： 为了减少同步型存储器件的测试时间，压缩电路将输入到数据输出端子的多个读寄存器中输入的多个存储单元数据压缩为1位数据。 存储体选择电路选择存储体#A或存储体#B的压缩电路的输出。 三态反相缓冲器根据测试模式命令信号传递由存储体选择电路选择的1位压缩数据。 数据输出端输出多个位的存储单元的压缩数据。 因此，可以同时确定多个存储单元的通过/失败，从而减少测试时间。

公开(公告)号：US20120016067A1

公开(公告)日：2012-01-19

申请号：US13260016

申请日：2010-08-04

申请人： Keisuke Masuko ,  Yasuhiro Fukudome ,  Yusuke Onodo ,  Seiji Sawada ,  Satoshi Ooi ,  Hideki Takahashi

发明人： Keisuke Masuko ,  Yasuhiro Fukudome ,  Yusuke Onodo ,  Seiji Sawada ,  Satoshi Ooi ,  Hideki Takahashi

IPC分类号： C09J11/04 ,  C09J133/10 ,  C09J133/08 ,  C09J131/04 ,  C09J133/12

CPC分类号： C08L23/0869 ,  C08K3/22 ,  C08K2003/2217 ,  C08K2003/2224 ,  C08K2003/2227 ,  C08L23/08 ,  C08L23/0861 ,  H01L31/048 ,  H01L31/0481 ,  Y02E10/50 ,  C08L2666/02

摘要： To achieve improvement in initial conversion efficiency of solar cell modules, inhibition of deterioration in transparency of a resin, inhibition of degradation in adhesive properties with respect to a protective member over time, and inhibition of degradation in conversion efficiency. A resin composition for solar cell-sealing material according to the present invention includes an ethylene copolymer, and further includes at least one of: (i) a compound represented by the following general formula (1); (ii) a calcined product of the (i); (iii) a compound represented by the following general formula (2); and (iv) a calcined product of the (iii). The (i) has an average plate surface diameter of 0.01 to 0.9 μm and a refractive index of 1.45 to 1.55, and the (iii) has an average plate surface diameter of 0.02 to 0.9 μm and a refractive index of 1.48 to 1.6. Mg1-n.Ala(OH)2.Ann−a/n.bH2O  General formula (1) (0.25≦a≦0.35, 0≦b≦1, An: an n-valent anion); (McMg1-c)1-d.Ald(OH)2.Bmm−d/m.eH2O  General formula (2) (M represents a metal selected from the group consisting of Ni, Zn, and Ca; c, d, and e are respectively expressed as 0.2≦c≦1, 0.2≦d≦0.4, and 0≦e≦4; Bm: an m-valent anion).

摘要翻译： 为了实现太阳能电池模块的初始转换效率的提高，抑制树脂透明度的劣化，抑制随着时间的流逝对粘合剂性能的影响，以及抑制转化效率降低。 根据本发明的太阳能电池密封材料用树脂组合物包括乙烯共聚物，并且还包括以下至少一种：（i）由以下通式（1）表示的化合物; （ii）（i）的煅烧产物; （iii）由以下通式（2）表示的化合物： 和（iv）（iii）的煅烧产物。 （i）的平均板表面直径为0.01〜0.9μm，折射率为1.45〜1.55，（iii）的平均板的表面直径为0.02〜0.9μm，折射率为1.48〜1.6。 Mg1-n.Ala（OH）2.Ann-a / n.bH2O通式（1）（0.25＆nlE; a＆nlE; 0.35,0和nlE; b＆nlE; 1，An：n价阴离子）; （McMg1-c）1-d.Ald（OH）2.Bmm-d / m.eH2O通式（2）（M表示选自Ni，Zn和Ca的金属; c，d和 e分别表示为0.2＆nlE; c＆nlE; 1,0.2＆amp; nlE; d＆nlE; 0.4和0＆amp; nlE; e＆nlE; 4; Bm：m价阴离子）。

公开(公告)号：US07908057B2

公开(公告)日：2011-03-15

申请号：US11559668

申请日：2006-11-14

申请人： Seiji Sawada ,  Takayuki Kifuku

发明人： Seiji Sawada ,  Takayuki Kifuku

IPC分类号： B62D5/04 ,  B62D6/10

CPC分类号： B62D5/0484 ,  B62D5/0472 ,  B62D5/049

摘要： Provided is a power steering apparatus capable of suppressing an abrupt change in steering force and preventing a deterioration in steering feeling even in the event of a transition from power steering to manual steering. The power steering apparatus includes a torque sensor, a motor of a permanent magnet field type, and a controller having a motor driving unit and an abnormality monitoring unit, for controlling the driving of the motor. The motor driving unit includes an inverter for driving the motor, and a drive signal generating unit for calculating a target current caused to flow through the motor and outputting a drive signal of the inverter based on the target current. The abnormality monitoring unit includes an abnormality processing unit for constituting a closed-loop circuit including the motor in stopping the driving of the motor.

摘要翻译： 提供一种能够抑制转向力的突然变化并且即使在从动力转向转换为手动转向的情况下也防止转向感觉的劣化的动力转向装置。 动力转向装置包括转矩传感器，永磁场型电动机和具有用于控制电动机的驱动的电动机驱动单元和异常监视单元的控制器。 马达驱动单元包括用于驱动马达的逆变器和驱动信号生成单元，用于计算通过马达流动的目标电流，并基于目标电流输出逆变器的驱动信号。 异常监视单元包括异常处理单元，用于在停止电动机的驱动时构成包括电动机的闭环电路。