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    Synchronous type semiconductor memory device operating in synchronization with an external clock signal
    1.
    发明授权
    Synchronous type semiconductor memory device operating in synchronization with an external clock signal 失效
    与外部时钟信号同步工作的同步型半导体存储器件

    公开(公告)号：US5404338A

    公开(公告)日：1995-04-04

    申请号：US189247

    申请日：1994-01-31

    申请人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

    发明人： Yasumitsu Murai ,  Hisashi Iwamoto ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

    IPC分类号： G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  F02B2075/027

    摘要： In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

    摘要翻译： 在同步半导体存储器件中，形成激活单元的存储器阵列（MA）被分成多个小存储器阵列（MK）。 提供了两个小型存储器阵列的本地I / O线对（LIO）。 跨字线的全局I / O线对（GIO）排列在字线分流区（WS）中。 连接开关（BS）布置在本地I / O线对与全局I / O线对之间的交叉中。 激活的存储器阵列中的每个小存储器阵列通过本地I / O线对连接到相应的全局I / O线对。 从而，可以同时读取多个比特，而不增加互连占用的面积。 使用读出放大器激活信号进行连接开关的控制。 数据传输到为数据输出端子提供的读数据寄存器用于顺序数据输出或选择存储单元时，全局I / O线被预充电/均衡。 外部时钟信号被分频以产生用于通过充电操作产生内部电压的相移内部时钟信号。

    Synchronous semiconductor memory device and synchronous memory module
    3.
    发明授权
    Synchronous semiconductor memory device and synchronous memory module 失效
    同步半导体存储器件和同步存储器模块

    公开(公告)号：US5815462A

    公开(公告)日：1998-09-29

    申请号：US800905

    申请日：1997-02-12

    申请人： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

    发明人： Yasuhiro Konishi ,  Hisashi Iwamoto ,  Takashi Araki ,  Yasumitsu Murai ,  Seiji Sawada

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/225 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/22

    摘要： A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.

    摘要翻译： 用于控制外部信号的输入和用于控制内部操作的第一时钟信号和用于控制数据输出的第二时钟信号分别被施加到分离的时钟输入节点。 可以调整相对于第一时钟信号的数据输出定时，从而可以调整时钟存取时间和数据保持时间。 内部数据读取路径被流水线化以包括响应于第一时钟信号的第一传送门，用于传送内部读取数据和第二传送门，响应于第二时钟信号，用于从第一传送门传送内部读取数据，以便通过 输出缓冲区。 提供一种同步半导体存储器件，其能够根据应用和减少时钟存取时间将时钟访问时间和数据保持时间设置在最佳值。

    Synchronous semiconductor memory device
    4.
    发明授权
    Synchronous semiconductor memory device 失效
    同步半导体存储器件

    公开(公告)号：US5592434A

    公开(公告)日：1997-01-07

    申请号：US548285

    申请日：1995-10-25

    申请人： Hisashi Iwamoto ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yasumitsu Murai

    发明人： Hisashi Iwamoto ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yasumitsu Murai

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C7/1048 ,  G11C7/1072

    摘要： To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.

    摘要翻译： 对于一个存储器阵列，两个系统中的全局信号输入/输出线对，用于以时钟周期交替地将全局IO线对连接到写缓冲器组的开关，以及用于将全局IO线对连接到等于 提供了基于时钟周期的交替电路。 在一个时钟周期内，可以并行执行通过一个全局IO线对写入数据和对另一个全局IO线对进行均衡。 因此，可以高频地容易地写入数据。

    Semiconductor memory device with an internal voltage generating circuit
    5.
    发明授权
    Semiconductor memory device with an internal voltage generating circuit 失效
    具有内部电压发生电路的半导体存储器件

    公开(公告)号：US06333873B1

    公开(公告)日：2001-12-25

    申请号：US08942692

    申请日：1997-09-29

    申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Kouji Hayano

    发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Kouji Hayano

    IPC分类号： G11C700

    CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C5/146 ,  G11C11/005

    摘要： A semiconductor memory device receives an external control signal repeatedly generated independently of an access to the memory device. The memory device includes an internal voltage generator for generating a desired internal voltage in response to the control signal. The internal voltage generator includes a charge pump circuit responsive to the control signal. The internal voltage may provide a negative voltage such as a substrate bias voltage, or may be a positive voltage boosted over an operating power supply voltage and used as a boosted word line drive signal. This scheme eliminates an oscillator for generating a repeated clock signal to the charge pump circuit, leading to reduced current consumption and reduced chip area for the semiconductor memory device.

    摘要翻译： 半导体存储器件接收独立于对存储器件的访问而重复产生的外部控制信号。 存储器件包括用于响应于控制信号产生期望的内部电压的内部电压发生器。 内部电压发生器包括响应于控制信号的电荷泵电路。 内部电压可以提供诸如衬底偏置电压的负电压，或者可以是在工作电源电压上升压的正电压并且用作升压的字线驱动信号。 该方案消除了用于向电荷泵电路产生重复时钟信号的振荡器，导致半导体存储器件的电流消耗降低和芯片面积减小。

    Synchronous semiconductor memory device reliably fetching external signal in synchronization with clock signal periodically supplied from the exterior
    6.
    发明授权
    Synchronous semiconductor memory device reliably fetching external signal in synchronization with clock signal periodically supplied from the exterior 失效
    同步半导体存储器件与从外部周期性提供的时钟信号同步地可靠地取得外部信号

    公开(公告)号：US5844859A

    公开(公告)日：1998-12-01

    申请号：US923689

    申请日：1997-09-04

    申请人： Hisashi Iwamoto ,  Yasuhiro Konishi

    发明人： Hisashi Iwamoto ,  Yasuhiro Konishi

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： When an operating frequency is increased and a CAS latency is set longer, a data write end time is delayed by a specific time in response to the change of the CAS latency. The specific time is greater than a period corresponding to the CAS latency. The specific time may be the minimum time necessary for writing second-bit data. The write margin can also be enlarged by delaying the write timing (activation and inactivation) in the interior of a memory itself by one clock cycle of an external clock signal. Thus, a write period for second-bit data is ensured in an SDRAM, even if the operation frequency is increased.

    摘要翻译： 当操作频率增加并且CAS延迟设置得更长时，响应于CAS延迟的改变，数据写入结束时间被延迟特定时间。 具体时间大于对应于CAS延迟的周期。 具体时间可以是写入第二位数据所需的最短时间。 也可以通过将外部时钟信号的一个时钟周期延迟存储器本身内部的写入定时（激活和去激活）来扩大写入裕度。 因此，即使操作频率增加，也可以在SDRAM中确保第二位数据的写周期。

    Synchronous semiconductor memory device
    7.
    发明授权
    Synchronous semiconductor memory device 失效
    同步半导体存储器件

    公开(公告)号：US5384745A

    公开(公告)日：1995-01-24

    申请号：US46333

    申请日：1993-04-14

    申请人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

    发明人： Yasuhiro Konishi ,  Takayuki Miyamoto ,  Takeshi Kajimoto ,  Hisashi Iwamoto

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C8/00

    CPC分类号： G11C7/1072 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12

    摘要： Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed. A synchronous semiconductor memory device having small chip area, high speed of operation, low power consumption and multiple functions is provided.

    摘要翻译： 存储器阵列被分成可以相互独立操作的存储体。 为银行提供读取数据存储寄存器和彼此独立操作的写入数据存储寄存器。 存储器阵列被分成多个小阵列块，对应于每个阵列块布置本地IO线，并且本地IO线连接到全局IO线。 全局IO线连接到前置放大器组并写入缓冲组。 通过控制信号发生电路和寄存器控制电路，可以仅在连续写入操作期间禁止对所需位的写入，如果数据写入应当是数据写入时，可以将数据集中写入所选存储单元 在连续写入之前到达卷绕长度之前停止，并且可以延迟在重复执行写入周期时激活存储器阵列的定时。 提供了具有小芯片面积，高运行速度，低功耗和多种功能的同步半导体存储器件。

    Synchronous semiconductor memory device
    8.
    发明授权
    Synchronous semiconductor memory device 失效
    同步半导体存储器件

    公开(公告)号：US5796669A

    公开(公告)日：1998-08-18

    申请号：US900123

    申请日：1997-07-25

    申请人： Takashi Araki ,  Hisashi Iwamoto ,  Yasuhiro Konishi

    发明人： Takashi Araki ,  Hisashi Iwamoto ,  Yasuhiro Konishi

    IPC分类号： G11C11/407 ,  G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C7/1063

    摘要： Switches (11, 12) select either of refresh address counters (6a, 6b) in accordance with a refresh bank set signal (.phi.REFADD) when a bank refresh signal (.phi.BANKREF) is activated. An internal bank address (int.BA) serves as the refresh bank set signal (.phi.REFADD) to control the switch (12) and the refresh address counter (6a or 6b) designated by the internal bank address (int.BA) performs a count operation in synchronization with a refresh clock (.phi.REFCLK). The switch (11) outputs either of refresh addresses (Ref.Add.sub.-- A , Ref.Add.sub.-- B ) which is updated. With this configuration provided is an SDRAM which allows access to data during a refresh operation.

    摘要翻译： 当bank刷新信号（phi BANKREF）被激活时，开关（11,12）根据刷新组设置信号（phi REFADD）来选择刷新地址计数器（6a，6b）。 内部银行地址（int.BA）用作刷新组设置信号（phi REFADD）以控制开关（12），由内部银行地址（int.BA）指定的刷新地址计数器（6a或6b）执行 计数操作与刷新时钟同步（phi REFCLK）。 开关（11）输出更新的刷新地址（Ref.Add-A <0:10>，Ref.Add-B <0:10>）。 提供这种配置是允许在刷新操作期间访问数据的SDRAM。