公开(公告)号：US09164834B2

公开(公告)日：2015-10-20

申请号：US14160614

申请日：2014-01-22

申请人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

发明人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

IPC分类号： G06F11/10 ,  G06F11/08 ,  G11C29/42

CPC分类号： G06F11/1056 ,  G06F11/085 ,  G06F11/1008 ,  G11C29/42

摘要： In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

摘要翻译： 在一个实施例中，半导体器件包括存储器阵列和被配置为控制从存储器阵列读取数据和将数据写入存储器阵列的控制架构。 控制架构被配置为在存储器阵列中接收数据和码字位置，基于数据掩码选择所接收数据中的一个或多个数据单元，读取当前存储在存储器阵列中的码字位置处的码字，错误校正 读取码字以产生经校正的读取码字，从所选择的数据单元中选出的数据单元形成一个新的码字，并且将校验后的读取码字中的数据单元与所选择的数据单元不对应，并将新的代码字写入存储器阵列。

公开(公告)号：US09588840B2

公开(公告)日：2017-03-07

申请号：US14225686

申请日：2014-03-26

申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

IPC分类号： G06F11/10 ,  G06F11/32

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

公开(公告)号：US5835400A

公开(公告)日：1998-11-10

申请号：US947607

申请日：1997-10-09

申请人： Byung-gil Jeon ,  Chul-sung Park

发明人： Byung-gil Jeon ,  Chul-sung Park

IPC分类号： G11C14/00 ,  G11C7/00 ,  G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices contain an array of ferroelectric memory cells therein and control circuits for enabling the performance of nondestructive read operations. The memory cells of a device contain a ferroelectric memory cell and each memory cell contains a ferroelectric capacitor having a first electrode electrically coupled to a plate line and an access transistor electrically coupled in series between a bit line and a second electrode of the ferroelectric capacitor. A decoder circuit is also provided. The decoder circuit is electrically coupled to the access transistor of the memory cell by a word line and performs the function of, among other things, turning on the access transistor during a read time interval. According to a preferred aspect of the present invention, a pulse generator circuit is provided for initiating nondestructive reading of a quiescent polarization state of the ferroelectric capacitor by applying a single read pulse to the plate line to sweep a polarization state of the ferroelectric capacitor along a noncoercive portion of its hysteresis curve, during the read time interval. A sense amplifier circuit is also provided. The sense amplifier circuit also has a first input electrically coupled to the bit line and a second input electrically coupled to a reference signal line. The sense amplifier performs the function of driving the bit line to a first potential which represents the quiescent polarization state of the ferroelectric capacitor, preferably before termination of the single read pulse.

摘要翻译： 铁电存储器件包含其中的铁电存储器单元阵列和用于实现非破坏性读取操作的控制电路。 器件的存储单元包含铁电存储单元，并且每个存储单元包含铁电电容器，该铁电电容器具有电耦合到板线的第一电极和电阻耦合在铁电电容器的位线和第二电极之间的存取晶体管。 还提供一个解码器电路。 解码器电路通过字线电耦合到存储单元的存取晶体管，并且执行在读取时间间隔期间接通存取晶体管的功能。 根据本发明的优选方面，提供了一种脉冲发生器电路，用于通过向板线施加单个读取脉冲来对铁电电容器的静态极化状态进行非破坏性读取，以扫描强电介质电容器的极化状态沿着 在读取时间间隔期间其滞后曲线的非矫正部分。 还提供读出放大器电路。 感测放大器电路还具有电耦合到位线的第一输入和电耦合到参考信号线的第二输入。 读出放大器执行将位线驱动到表示铁电电容器的静态极化状态的第一电位的功能，优选在单个读取脉冲结束之前。

公开(公告)号：US10067681B2

公开(公告)日：2018-09-04

申请号：US13427625

申请日：2012-03-22

申请人： Chul-sung Park ,  Joo-sun Choi

发明人： Chul-sung Park ,  Joo-sun Choi

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C7/10 ,  G11C8/10

摘要： A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

公开(公告)号：US20120303870A1

公开(公告)日：2012-11-29

申请号：US13427625

申请日：2012-03-22

申请人： Chul-sung Park ,  Joo-sun Choi

发明人： Chul-sung Park ,  Joo-sun Choi

IPC分类号： G06F12/00

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G11C7/10 ,  G11C8/10 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5621 ,  G11C11/565 ,  G11C11/5678 ,  G11C11/5685 ,  G11C2211/5641 ,  G11C2213/71

摘要： A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

摘要翻译： 存储器芯片，存储器系统和访问存储器芯片的方法。 存储芯片包括基板，第一存储单元和第二存储单元。 第一存储单元包括多个第一存储单元可以具有2n的第一存储容量。 多个第一存储器单元可以被配置为响应于第一选择信号而被激活。 第二存储单元包括多个第二存储单元，并且可以具有2n + 1的第二存储容量。 多个第二存储器单元可以被配置为响应于第二选择信号来激活。

公开(公告)号：US20080072121A1

公开(公告)日：2008-03-20

申请号：US11750527

申请日：2007-05-18

申请人： Seung-min Lee ,  Chul-sung Park ,  Young-seung Kim ,  Byeong-uk Yoo

发明人： Seung-min Lee ,  Chul-sung Park ,  Young-seung Kim ,  Byeong-uk Yoo

IPC分类号： G06F11/16

CPC分类号： G11C29/812 ,  G11C29/806 ,  G11C29/808

摘要： A method and apparatus for repairing defective cells for each section word line. The repairing apparatus includes an address comparison unit and a repairing unit. The address comparison unit compares a main address of a defective address, indicating the location of a defective cell, to a main address of an external address. The address comparison unit determines when a redundancy main word line corresponding to the main address of the external address is activated. The repairing unit activates a redundancy section word line corresponding to a section address of the external address from among a plurality of redundancy section word lines connected to the redundancy main word line in order to repair the defective cell. Accordingly, defective cells are repaired for each section word line while minimizing the area of the repairing apparatus. Randomly generated defective cells can be efficiently repaired.

摘要翻译： 一种用于修复每个部分字线的有缺陷的单元的方法和装置。 修理装置包括地址比较单元和修理单元。 地址比较单元将指示缺陷单元的位置的缺陷地址的主地址与外部地址的主地址进行比较。 地址比较单元确定何时激活对应于外部地址的主地址的冗余主字线。 修复单元从与冗余主字线连接的多个冗余部分字线中激活对应于外部地址的部分地址的冗余部分字线，以便修复有缺陷的单元。 因此，对于每个部分字线修复有缺陷的单元，同时最小化修复装置的面积。 随机产生的有缺陷的细胞可以被有效地修复。

公开(公告)号：US07340560B2

公开(公告)日：2008-03-04

申请号：US10896719

申请日：2004-07-22

申请人： Byong-kwon Lee ,  Cheol-Shin Kwak ,  Chul-sung Park

发明人： Byong-kwon Lee ,  Cheol-Shin Kwak ,  Chul-sung Park

IPC分类号： G06F12/00

CPC分类号： G11C8/12 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C11/418

摘要： A method of accessing an integrated circuit memory device can include reading from an address in a first memory sub-block during a first clock cycle. The address of a first data memory block address mapped to the first memory sub-block can be written to during the first clock cycle. The address of a second data memory block address mapped can be written to the second memory sub-block during a second clock cycle immediately subsequent in time to the first clock cycle. Related device are disclosed.

摘要翻译： 访问集成电路存储器件的方法可以包括在第一时钟周期期间从第一存储器子块中的地址读取。 映射到第一存储器子块的第一数据存储器块地址的地址可以在第一时钟周期期间被写入。 第二数据存储器块地址映射的地址可以在紧接着到第一时钟周期的时间之后的第二时钟周期期间写入第二存储器子块。 公开了相关设备。

公开(公告)号：US20050018521A1

公开(公告)日：2005-01-27

申请号：US10896719

申请日：2004-07-22

申请人： Byong-kwon Lee ,  Cheol-Shin Kwak ,  Chul-sung Park

发明人： Byong-kwon Lee ,  Cheol-Shin Kwak ,  Chul-sung Park

IPC分类号： G11C11/40 ,  G06F12/08 ,  G11C8/12 ,  G11C11/418 ,  G11C8/00

CPC分类号： G11C8/12 ,  G06F12/0893 ,  G06F2212/3042 ,  G11C11/418

摘要： A method of accessing an integrated circuit memory device can include reading from an address in a first memory sub-block during a first clock cycle. The address of a first data memory block address mapped to the first memory sub-block can be written to during the first clock cycle. The address of a second data memory block address mapped can be written to the second memory sub-block during a second clock cycle immediately subsequent in time to the first clock cycle. Related device are disclosed.

摘要翻译： 访问集成电路存储器件的方法可以包括在第一时钟周期期间从第一存储器子块中的地址读取。 映射到第一存储器子块的第一数据存储器块地址的地址可以在第一时钟周期期间被写入。 第二数据存储器块地址映射的地址可以在紧接着到第一时钟周期的时间之后的第二时钟周期期间写入第二存储器子块。 公开了相关设备。