公开(公告)号：US09164834B2

公开(公告)日：2015-10-20

申请号：US14160614

申请日：2014-01-22

申请人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

发明人： Hoi-ju Chung ,  Chul-sung Park ,  Jae-Wook Lee ,  Jang-Woo Ryu ,  Tae-seong Jang ,  Gong-heum Han

IPC分类号： G06F11/10 ,  G06F11/08 ,  G11C29/42

CPC分类号： G06F11/1056 ,  G06F11/085 ,  G06F11/1008 ,  G11C29/42

摘要： In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

摘要翻译： 在一个实施例中，半导体器件包括存储器阵列和被配置为控制从存储器阵列读取数据和将数据写入存储器阵列的控制架构。 控制架构被配置为在存储器阵列中接收数据和码字位置，基于数据掩码选择所接收数据中的一个或多个数据单元，读取当前存储在存储器阵列中的码字位置处的码字，错误校正 读取码字以产生经校正的读取码字，从所选择的数据单元中选出的数据单元形成一个新的码字，并且将校验后的读取码字中的数据单元与所选择的数据单元不对应，并将新的代码字写入存储器阵列。

公开(公告)号：US09588840B2

公开(公告)日：2017-03-07

申请号：US14225686

申请日：2014-03-26

申请人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

发明人： Hoi-ju Chung ,  Chul-sung Park ,  Tae-young Oh ,  Jang-woo Ryu ,  Chan-yong Lee ,  Tae-seong Jang ,  Gong-heum Han

IPC分类号： G06F11/10 ,  G06F11/32

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076

摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

摘要翻译： 一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后 在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

公开(公告)号：US06590434B2

公开(公告)日：2003-07-08

申请号：US10191413

申请日：2002-07-10

申请人： Hoe-ju Chung ,  Tae-seong Jang ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Tae-seong Jang ,  Kyu-hyoun Kim

IPC分类号： H03H1126

CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00091 ,  H03L7/0814

摘要： A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

公开(公告)号：US5946269A

公开(公告)日：1999-08-31

申请号：US156345

申请日：1998-09-18

申请人： Tae-seong Jang

发明人： Tae-seong Jang

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/04 ,  G11C11/407 ,  H03M7/00 ,  G11C8/00

CPC分类号： G11C7/1018

摘要： There are provided a synchronous RAM controlling device and method for controlling a synchronous RAM in order to access data when a burst length of a memory access is full page regardless of whether a termination access method or a wrap-around access method is used. In the synchronous RAM controlling device, an OR gate performs an OR operation on a burst stop signal for stopping input/output of data in the synchronous RAM responsive to an externally received input/output operation command signal. A counter is reset in response to the OR-operation result and counts the cycles of an external system clock signal. A burst sensor senses completion of a burst operation according to a burst length signal which is externally received and represents a burst length of at least 1 and outputs the sensed result as the burst stop signal. A control signal is input to the burst sensor which causes the burst sensor to operate the memory in one of termination or wrap-around access methods. A controller outputs the control signal, where the value of the control signal indicates termination access method when a fuse of the controller is not cut and either no logic level or a high logic level are input to an input pad of the controller. When the fuse is cut or a logic low level is input to the input pad, then the control signal output by the controller will indicate wrap-around access method.

摘要翻译： 提供了一种用于控制同步RAM的同步RAM控制装置和方法，以便当存储器访问的突发长度是全页时访问数据，而不管终端访问方法还是环绕访问方法是否被使用。 在同步RAM控制装置中，OR门响应于外部接收的输入/输出操作命令信号，对突发停止信号执行OR操作，以停止同步RAM中的数据的输入/输出。 计数器响应于或运算结果而复位，并对外部系统时钟信号的周期进行计数。 突发传感器根据外部接收的突发长度信号来感测突发操作的完成，并且表示至少为1的突发长度，并将感测结果输出为突发停止信号。 控制信号被输入到突发传感器，其使得突发传感器以终止或环绕访问方法之一来操作存储器。 控制器输出控制信号，其中控制信号的值表示当控制器的熔丝没有被切断并且没有逻辑电平或高逻辑电平被输入到控制器的输入焊盘时的终止访问方法。 当熔断器被切断或逻辑低电平输入到输入焊盘时，控制器输出的控制信号将指示环绕存取方式。

公开(公告)号：US20130016574A1

公开(公告)日：2013-01-17

申请号：US13548484

申请日：2012-07-13

申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC分类号： G11C29/08 ,  G11C7/00

CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US5959936A

公开(公告)日：1999-09-28

申请号：US977187

申请日：1997-11-24

申请人： Dong-il Seo ,  Tae-seong Jang

发明人： Dong-il Seo ,  Tae-seong Jang

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/413 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A column select line enable circuit prevents the first bit in a sequence of output data from being missed, thereby reducing tRCD in a synchronous memory device. The circuit delays a predetermined period of time after a row active command is applied to the memory device and then activates a column select enable line regardless of the state of the system clock signal. The column select enable line is maintained in an active state for a second period of time to allow the first bit of data to be read from the device. Thereafter, the column select enable line is enabled and disabled responsive to the system clock signal to read the remaining bits in the sequence of output data in a conventional manner. In a preferred embodiment, the circuit does not enable the column select enable line unless a decoded bank address signal is active.

摘要翻译： 列选择线使能电路防止输出数据序列中的第一位被错过，从而减少同步存储器件中的tRCD。 在将行活动命令施加到存储器件之后，电路延迟预定的时间段，然后激活列选择使能线，而不管系统时钟信号的状态如何。 列选择使能线在第二时间段内保持在活动状态，以允许从设备读取第一位数据。 此后，响应于系统时钟信号，列选择使能线被使能和禁止，以常规方式读出输出数据序列中的剩余位。 在优选实施例中，除非解码的存储体地址信号有效，否则该电路不启用列选择使能线。

公开(公告)号：US06329863B1

公开(公告)日：2001-12-11

申请号：US09477235

申请日：2000-01-04

申请人： Seung-hoon Lee ,  Tae-seong Jang

发明人： Seung-hoon Lee ,  Tae-seong Jang

IPC分类号： H03K508

CPC分类号： H01L23/50 ,  H01L23/5256 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having an input circuit well-suited for use in a stacked-chip configuration, results in a reduction in input capacitance, and an overall improvement in transmission speed. The semiconductor device includes at least two bonding pads which receive external electrical input signals from a shared common external pin, and at least two internal circuits, each electrically coupled to a corresponding bonding pad by a signal transmission line. The semiconductor device further includes at least two protective elements, each electrically coupled to a corresponding signal transmission line, each for protecting the internal circuits from excessive electrical transmission characteristics in the input signal. At least two fuses are electrically coupled in series between the corresponding protective element and signal transmission line. The fuses are each capable of being opened to electrically insulate the protective elements from the bonding pads and the internal circuits. By keeping only one fuse active, and opening the rest, the overall system capacitance, as viewed by the common external pin, is greatly reduced.

摘要翻译： 具有非常适合用于堆叠芯片配置的输入电路的半导体器件导致输入电容的降低和传输速度的总体改善。 半导体器件包括至少两个接合焊盘，其接收来自共用公共外部引脚的外部电输入信号，以及至少两个内部电路，每个内部电路通过信号传输线电耦合到对应的焊盘。 半导体器件还包括至少两个保护元件，每个保护元件电耦合到对应的信号传输线，每个保护元件用于保护内部电路免于输入信号中的过大的电传输特性。 至少两个保险丝串联在相应的保护元件和信号传输线之间。 保险丝均能够被打开以将保护元件与接合焊盘和内部电路电绝缘。 通过保持只有一个保险丝激活，并打开其余的，由公共外部引脚所看到的整个系统电容大大减少。

公开(公告)号：US06301170B2

公开(公告)日：2001-10-09

申请号：US09766733

申请日：2001-01-22

申请人： Tae-seong Jang

发明人： Tae-seong Jang

IPC分类号： G11C700

CPC分类号： G11C29/32 ,  G11C2029/1202 ,  G11C2029/2602

摘要： A multi-row active disturb (MRAD) test circuit, a semiconductor memory device having the test circuit, and an MRAD test method are provided. The semiconductor memory device includes at least one memory array including a plurality of word lines sharing a bit line sense amplifier. Furthermore, in the semiconductor memory device, at least two word lines among the plurality of word lines, which have a bit line sense amplifier in common, are activated simultaneously in an MRAD test mode. The test circuit includes a control signal generating circuit and a row decoder. The control signal generating circuit is a circuit for generating a plurality of control signals and generates at least one activated control signal in an MRAD test mode. The row decoder activates at least two word lines by a control signal and a predetermined row address signal comprised of a plurality of bits. The test circuit and the test method provide a reduction in test time for a semiconductor memory device without increase in current consumption.

摘要翻译： 提供多行有源干扰（MRAD）测试电路，具有测试电路的半导体存储器件和MRAD测试方法。 半导体存储器件包括至少一个包括共享位线读出放大器的多个字线的存储器阵列。 此外，在半导体存储器件中，具有位线读出放大器的多个字线中的至少两个字线在MRAD测试模式中同时被激活。 测试电路包括控制信号发生电路和行解码器。 控制信号发生电路是用于产生多个控制信号并在MRAD测试模式中产生至少一个激活的控制信号的电路。 行解码器通过控制信号和由多个位组成的预定行地址信号来激活至少两个字线。 测试电路和测试方法提供半导体存储器件的测试时间的减少，而不增加电流消耗。

公开(公告)号：US09036439B2

公开(公告)日：2015-05-19

申请号：US13548484

申请日：2012-07-13

申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

IPC分类号： G11C29/08 ,  G11C7/00 ,  G11C29/50 ,  G11C11/406 ,  G11C5/04 ,  G11C11/40

CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

公开(公告)号：US6031786A

公开(公告)日：2000-02-29

申请号：US134807

申请日：1998-08-14

申请人： Tae-seong Jang ,  Sung-keun Lee

发明人： Tae-seong Jang ,  Sung-keun Lee

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C29/12 ,  G11C13/00

CPC分类号： G11C7/22 ,  G11C8/18

摘要： An operation control circuit of an integrated circuit memory device operates in a synchronous mode according to an internal clock signal. An internal clock controller generates an internal clock enable signal in response to a mode command. An internal clock generator generates the internal clock signal based on the internal clock enable signal and an external clock. In particular, an internal clock controller generates an internal clock enable signal in response to a mode command. Accordingly, the integrated circuit memory device may be free of a clock enable pin.

摘要翻译： 集成电路存储器件的操作控制电路根据内部时钟信号在同步模式下工作。 内部时钟控制器响应于模式命令产生内部时钟使能信号。 内部时钟发生器根据内部时钟使能信号和外部时钟产生内部时钟信号。 特别地，内部时钟控制器响应于模式命令产生内部时钟使能信号。 因此，集成电路存储器件可以没有时钟使能引脚。