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    Semiconductor device structure and methods of manufacturing the same
    1.
    发明申请
    Semiconductor device structure and methods of manufacturing the same 有权
    半导体器件结构及其制造方法

    公开(公告)号：US20070166887A1

    公开(公告)日：2007-07-19

    申请号：US11333618

    申请日：2006-01-17

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    IPC分类号： H01L21/82

    CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

    摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

    Semiconductor device structure and methods of manufacturing the same
    4.
    发明授权
    Semiconductor device structure and methods of manufacturing the same 有权
    半导体器件结构及其制造方法

    公开(公告)号：US07512924B2

    公开(公告)日：2009-03-31

    申请号：US11333618

    申请日：2006-01-17

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

    摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

    Method for designing interconnect for a new processing technology
    5.
    发明申请
    Method for designing interconnect for a new processing technology 审中-公开
    用于设计新加工技术的互连的方法

    公开(公告)号：US20070158835A1

    公开(公告)日：2007-07-12

    申请号：US11332566

    申请日：2006-01-12

    申请人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

    发明人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.

    摘要翻译： 公开了一种用于在从参考处理技术缩放到预定处理技术的同时，分别在集成电路的两层中确定第一和第二导体之间的互连尺寸的方法。 该方法包括基于预定的处理技术来选择一组导体的设计规则，基于设计规则确定互连的矩形横截面积的第一侧的长度，以及用于缩放这种长度的缩放规则 将参考处理技术应用于预定处理技术，以及确定互连横截面积的第二侧的长度，以补偿由于从参考处理技术到预定处理技术的缩放而导致的互连电阻的增加 。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090200549A1

    公开(公告)日：2009-08-13

    申请号：US12426995

    申请日：2009-04-21

    申请人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

    发明人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

    IPC分类号： H01L23/00

    CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

    摘要翻译： 公开了一种半导体器件。 该器件包括衬底和覆盖衬底的第一布线层。 第一布线层包括由第一密封环包围的第一布线区域。 第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。 第一监视器电路响应于在第三电介质层中发生预定量的变形。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20080296570A1

    公开(公告)日：2008-12-04

    申请号：US11754394

    申请日：2007-05-29

    申请人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

    发明人： Hsien-Wei Chen ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

    IPC分类号： H01L23/58

    CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer.

    摘要翻译： 公开了一种半导体器件。 该器件包括衬底和覆盖衬底的第一布线层。 第一布线层包括由第一密封环包围的第一布线区域。 第一密封环包括由嵌入在第一密封环中的第一介电层隔离的第一监测电路。 第一监视器电路响应于在第三电介质层中发生预定量的变形。

    METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE 有权
    用于制造半导体器件的空气隙的方法

    公开(公告)号：US20080076258A1

    公开(公告)日：2008-03-27

    申请号：US11533809

    申请日：2006-09-21

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7682 ,  H01L21/0206

    摘要： A method for fabricating an interconnect structure in a semiconductor device. A masking layer is formed on a dielectric layer formed on a substrate, having at least one opening. The opening is transferred into the dielectric layer. A Plasma stripping process is performed to remove the masking layer, such that a damaged sidewall portion of the dielectric layer surrounding the opening therein is formed. The opening in the dielectric layer is filled with a conductive element. The damaged sidewall portion of the dielectric layer is removed to form a gap between the dielectric layer and the conductive element, wherein substances from removal of the damaged sidewall portion of the dielectric layer are formed on the conductive element. The substances are removed using a citric acid solution.

    摘要翻译： 一种在半导体器件中制造互连结构的方法。 在形成在基板上的电介质层上形成有至少一个开口的掩模层。 开口转移到电介质层中。 进行等离子体剥离处理以去除掩模层，从而形成围绕其中的开口的电介质层的受损侧壁部分。 电介质层中的开口填充有导电元件。 去除电介质层损坏的侧壁部分，以形成电介质层和导电元件之间的间隙，其中去除导电元件上介质层损坏的侧壁部分的物质。 使用柠檬酸溶液除去物质。

    Design structure for coupling noise prevention
    10.
    发明申请
    Design structure for coupling noise prevention 有权

    公开(公告)号：US20060244133A1

    公开(公告)日：2006-11-02

    申请号：US11119868

    申请日：2005-05-02

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen

    IPC分类号： H01L23/34

    CPC分类号： H01L23/5225 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure for preventing coupling noise in integrated circuits and a method of forming the same are provided. The semiconductor structure includes a signal-grounded seal ring. The seal ring includes a plurality of metal lines, each in a respective metal layer and surrounding a circuit region of the semiconductor chip, a plurality of vias connecting respective metal lines, and a plurality of dielectric layers isolating each metal layer from any other metal layers. The seal ring may further include additional seal rings formed inside or outside the seal ring. The semiconductor structure may include laser fuses and protective rings. The protective rings are preferably signal grounded. Cross talk between sub circuits in a chip can be reduced by forming a seal ring extension between the sub circuits.