公开(公告)号：US06774007B2

公开(公告)日：2004-08-10

申请号：US10244988

申请日：2002-09-17

申请人： Hsien-Wen Liu ,  Hui Min Mao ,  Yi-Nan Chen ,  Yi-Chen Chen

发明人： Hsien-Wen Liu ,  Hui Min Mao ,  Yi-Nan Chen ,  Yi-Chen Chen

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method of fabricating shallow trench isolation. In the method, a refill step of oxide layer and a step of forming a sacrificial layer on the semiconductor substrate are applied after filling insulating layer into the shallow trenches. The purpose of the steps is to protect the oxide layer on the semiconductor substrate and the corner of the shallow trenches, used to isolate the STI.

摘要翻译： 一种制造浅沟槽隔离的方法。 在该方法中，在将绝缘层填充到浅沟槽中之后，施加氧化物层的再填充步骤和在半导体衬底上形成牺牲层的步骤。 步骤的目的是保护用于隔离STI的半导体衬底上的氧化物层和浅沟槽的角部。

公开(公告)号：US07285377B2

公开(公告)日：2007-10-23

申请号：US10715616

申请日：2003-11-18

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： G03F7/00

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US07009236B2

公开(公告)日：2006-03-07

申请号：US10691173

申请日：2003-10-22

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US20050277287A1

公开(公告)日：2005-12-15

申请号：US11019850

申请日：2004-12-21

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： G03F9/00 ,  H01L21/00 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/544

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

摘要翻译： 一种使用多层硬掩模形成接触孔的方法。 提供了具有器件区域和其中具有开口的对准区域用作对准标记的衬底。 形成覆盖在基板上的电介质层，并填充开口，随后是多层硬掩模。 开口上的多层硬掩模被部分去除，并且在器件区域上被图案化以在其中形成多个孔并且暴露下面的介电层。 在器件区域上暴露的介电层被蚀刻以在其中形成多个接触孔。

公开(公告)号：US20050275111A1

公开(公告)日：2005-12-15

申请号：US10923585

申请日：2004-08-20

申请人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

发明人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

摘要翻译： 使用部分凹入的硬掩模形成接触孔的方法。 提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。 形成覆盖在基板上并填充开口的电介质层。 在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。 蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。

公开(公告)号：US20050106887A1

公开(公告)日：2005-05-19

申请号：US10783467

申请日：2004-02-20

申请人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76897

摘要： A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.

摘要翻译： 一种形成接触孔的方法。 提供形成有多个栅极结构的基板，其中栅极结构包括栅极，栅极覆盖层和栅极间隔物。 在栅极结构上形成绝缘层，并填充在栅极结构之间。 使用栅极覆盖层，栅极间隔物和衬底作为停止层来蚀刻绝缘层，以在栅极结构之间形成第一接触孔，以暴露衬底和栅极间隔物，并形成覆盖每个栅极结构的第二接触孔，以暴露出 门盖层。 在第一接触孔和第二接触孔的每个侧壁上形成保护隔离物。 在每个栅极接触孔下方的栅极覆盖层使用保护隔板作为停止层进行蚀刻，以露出栅极。 去除保护性间隔物。

公开(公告)号：US06709975B2

公开(公告)日：2004-03-23

申请号：US10222349

申请日：2002-08-16

申请人： Hui Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Hui Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76837 ,  H01L21/76885

摘要： A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

摘要翻译： 一种形成金属间电介质（IMD）的方法。 其上具有图案化金属层的衬底具有至少一个露出衬底的开口。 开口的长宽比为3.5〜4.5。 接下来，开口填充有第一电介质层，并且由于高纵横比开口，在第一电介质层的上部形成空隙。 此后，蚀刻第一电介质层以使第一介电层在开口中具有预定的高度而没有空隙。 最后，在第一电介质层上形成第二电介质层以完全填充开口。

公开(公告)号：US07678692B2

公开(公告)日：2010-03-16

申请号：US11564238

申请日：2006-11-28

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US07211483B2

公开(公告)日：2007-05-01

申请号：US11068173

申请日：2005-02-28

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US07135783B2

公开(公告)日：2006-11-14

申请号：US10923585

申请日：2004-08-20

申请人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

发明人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L23/544 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/544 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

摘要翻译： 使用部分凹入的硬掩模形成接触孔的方法。 提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。 形成覆盖在基板上并填充开口的电介质层。 在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。 蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。