公开(公告)号：US06867078B1

公开(公告)日：2005-03-15

申请号：US10716955

申请日：2003-11-19

申请人： Bruce M. Green ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Y. Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

发明人： Bruce M. Green ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Y. Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

IPC分类号： H01L21/335 ,  H01L29/423 ,  H01L29/778 ,  H01L21/338 ,  H01L21/3205

CPC分类号： H01L29/66462 ,  H01L29/42316 ,  H01L29/7785

摘要： A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1−xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

摘要翻译： 微波场效应晶体管（10）具有覆盖具有未掺杂沟道层（18）的双异质结结构（14,18,22）的高导电性栅极（44）。 异质结结构覆盖在基板（12）上。 作为非有意掺杂（NID）层（24）的凹陷层覆盖在异质结结构上并形成预定的厚度，使得在源极/漏极欧姆接触（30）的漏极接触的界面处的冲击电离效应最小化并允许 比上一级栅晶体管显着更高的电压操作。 另一个凹陷层（26）用于限定门尺寸。 肖特基门开口（42）形成在步进门开口（40）内以形成阶梯门结构。 使用In x Ga 1-x As的沟道层（18）材料来提供具有改善的传输特性的电子约束区域，这导致更高的操作频率，更高的功率密度和更好的功率附加效率。

公开(公告)号：US07229903B2

公开(公告)日：2007-06-12

申请号：US10925855

申请日：2004-08-25

申请人： Hsin-Hua P. Li ,  Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Charles E. Weitzel

发明人： Hsin-Hua P. Li ,  Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Charles E. Weitzel

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7785 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer. A first conductive portion is coupled to the first semiconductor layer, and a second conductive portion is formed over the first semiconductor layer.

摘要翻译： 半导体结构包括第一半导体层，第一半导体层上的第二半导体层，第二半导体层上的第三半导体层以及第三半导体层上的第四半导体层。 第一导电部分耦合到第一半导体层，并且在第一半导体层上形成第二导电部分。

公开(公告)号：US07253455B2

公开(公告)日：2007-08-07

申请号：US11100095

申请日：2005-04-05

申请人： Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Philip H. Li ,  Monte G. Miller ,  Matthias Passlack ,  Marcus R. Ray ,  Charles E. Weitzel

发明人： Bruce M. Green ,  Olin L. Hartin ,  Ellen Y. Lan ,  Philip H. Li ,  Monte G. Miller ,  Matthias Passlack ,  Marcus R. Ray ,  Charles E. Weitzel

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L29/06

CPC分类号： H01L29/7785

摘要： In one embodiment, a semiconductor device (500) includes a buffer layer (504) formed over a substrate (502). An AlxGa1−xAs layer (506) is formed over the buffer layer (504) and has a first doped region (508) formed therein. An InxGa1−xAs channel layer (512) is formed over the AlxGa1−xAs layer (506). An AlxGa1−xAs layer (518) is formed over the InxGa1−xAs channel layer (512), and the AlxGa1−xAs layer (518) has a second doped region formed therein. A GaAs layer (520) having a first recess is formed over the AlxGa1−xAs layer (518). A control electrode (526) is formed over the AlxGa1−xAs layer (518). A doped GaAs layer (524) is formed over the undoped GaAs layer (520) and on opposite sides of the control electrode (526) and provides first and second current electrodes. When used to amplify a digital modulation signal, the semiconductor device (500) maintains linear operation over a wide temperature range.

摘要翻译： 在一个实施例中，半导体器件（500）包括形成在衬底（502）上的缓冲层（504）。 在缓冲层（504）之上形成Al x Ga 1-x As层（506），并且在其中形成有第一掺杂区域（508）。 在Al x Ga 1-x 上形成一个In 1 / x Ga 1-x As As沟道层（512） >作为层（506）。 在In 1 x 1 Ga 1-x N上形成Al x Ga 1-x As层（518） 作为沟道层（512）和Al x Ga 1-x As层（518）具有形成在其中的第二掺杂区域。 具有第一凹陷的GaAs层（520）形成在Al 1 Ga 1-x As层（518）上。 控制电极（526）形成在Al 1 Ga 1-x As As层（518）上。 在未掺杂的GaAs层（520）上和控制电极（526）的相对侧上形成掺杂GaAs层（524），并提供第一和第二电流电极。 当用于放大数字调制信号时，半导体器件（500）在宽的温度范围内保持线性操作。

公开(公告)号：US10249615B2

公开(公告)日：2019-04-02

申请号：US14594286

申请日：2015-01-12

申请人： Bruce M. Green ,  James A. Teplik

发明人： Bruce M. Green ,  James A. Teplik

IPC分类号： H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/812 ,  H01L21/8258 ,  H01L27/088 ,  H01L29/78 ,  H01L29/20 ,  H01L29/51

摘要： A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

公开(公告)号：US08946776B2

公开(公告)日：2015-02-03

申请号：US13533610

申请日：2012-06-26

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L29/812

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

公开(公告)号：US08609538B2

公开(公告)日：2013-12-17

申请号：US13764398

申请日：2013-02-11

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields.

摘要翻译： 具有通过在后表面上的导体与衬底的前表面之间的导体之间延伸的导电衬底的电子器件包括在前表面导体下方的多层蚀刻停止。 蚀刻停止允许使用单个蚀刻剂来穿透基板和任何上覆的半导体和/或电介质，而不会攻击上覆的前表面导体。 当半导体和电介质如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止优选地是N> = 2对子层的堆叠，其中第一子层包括减轻应力和/或粘附促进材料（例如，Ti），并且第二子层包括耐蚀刻材料 （例如Ni）。 在另一实施例中，其中器件包括具有反馈敏感控制栅极的场效应晶体管，蚀刻停止材料有利地用于形成栅极屏蔽。

公开(公告)号：US20100295100A1

公开(公告)日：2010-11-25

申请号：US12469326

申请日：2009-05-20

申请人： JENN HWA HUANG ,  Bruce M. Green

发明人： JENN HWA HUANG ,  Bruce M. Green

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/812 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/66856 ,  H01L29/7786

摘要： A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

摘要翻译： 体GaN层位于衬底的第一表面上，其中体GaN层具有GaN晶体管区和体声波（BAW）器件区。 源极/漏极层在GaN晶体管区域中的体GaN层的第一表面之上。 在源极/漏极层上形成栅电极。 第一BAW电极形成在BAW器件区域中的体GaN层的第一表面上。 在衬底的与衬底的第一表面相对的第二表面上形成开口，该第一表面延伸穿过衬底并暴露与体GaN层的第一表面相对的体GaN层的第二表面。 在体GaN层的第二表面上的开口内形成第二BAW电极。

公开(公告)号：US20150132932A1

公开(公告)日：2015-05-14

申请号：US14601804

申请日：2015-01-21

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L21/285

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

公开(公告)号：US08946779B2

公开(公告)日：2015-02-03

申请号：US13777858

申请日：2013-02-26

申请人： Bruce M. Green ,  James A. Teplik

发明人： Bruce M. Green ,  James A. Teplik

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/812 ,  H01L29/80 ,  H01L29/20

CPC分类号： H01L27/0629 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7839 ,  H01L29/812

摘要： A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

摘要翻译： 半导体器件包括：衬底，其包括异质结构，该异质结构被配置为在操作期间支持通道的形成，由衬底支撑的第一和第二电介质层，第二介电层设置在第一介电层和衬底之间，栅极由衬底支撑 ，设置在所述第一介电层中的第一开口中，并且在操作期间施加偏置电压以控制通过所述沟道的电流，所述第二介电层设置在所述栅极和所述衬底之间，以及由所述衬底支撑的电极 ，设置在第一和第二电介质层中的第二开口中，并且被配置为与衬底建立肖特基结。

公开(公告)号：US08592878B2

公开(公告)日：2013-11-26

申请号：US13042948

申请日：2011-03-08

申请人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

发明人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC分类号： H01L29/66

CPC分类号： H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

摘要翻译： 实施例包括具有低泄漏肖特基接触的半导体器件。 通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。