公开(公告)号：US20150132932A1

公开(公告)日：2015-05-14

申请号：US14601804

申请日：2015-01-21

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L21/285

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

公开(公告)号：US06794101B2

公开(公告)日：2004-09-21

申请号：US10159909

申请日：2002-05-31

申请人： Lianjun Liu ,  Jenn-Hwa Huang ,  Lei Mercado ,  Shun-Meen Kuo

发明人： Lianjun Liu ,  Jenn-Hwa Huang ,  Lei Mercado ,  Shun-Meen Kuo

IPC分类号： G03G1304

CPC分类号： H01P1/127 ,  H01H59/0009 ,  H01H2001/0084

摘要： A micro-electro-mechanical device (10) including a shorting bar (40) having a first portion (42) electrically coupled to a first input/output signal line (34) and a second portion (43) electrically uncoupled to a second input/output signal line (36). Shorting bar (40) is coupled to a moveable end (49) of a cantilever structure (44). Thus, preferably only the second portion (43) of shorting bar (40) needs to be actuated to be electrically coupled to the second input/output signal line (36).

摘要翻译： 一种微电子机械装置（10），包括具有电耦合到第一输入/输出信号线（34）的第一部分（42）的短路棒（40）和与第二输入端 /输出信号线（36）。 短杆（40）联接到悬臂结构（44）的可移动端（49）。 因此，优选仅需要致动短路棒（40）的第二部分（43）以电耦合到第二输入/输出信号线（36）。

公开(公告)号：US06479843B2

公开(公告)日：2002-11-12

申请号：US09559791

申请日：2000-04-27

申请人： Jenn-Hwa Huang ,  Elizabeth C. Glass ,  Olin Hartin ,  Wendy L. Valentine ,  Julio Costa

发明人： Jenn-Hwa Huang ,  Elizabeth C. Glass ,  Olin Hartin ,  Wendy L. Valentine ,  Julio Costa

IPC分类号： H01L21338

CPC分类号： H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H03F1/301 ,  H03K17/145

摘要： A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

摘要翻译： 一种制造装置的方法和装置，用于在单个电源HFET中提供低电压温度补偿，所述单电源HFET包括在叠层中形成的具有HFET的外延生长的化合物半导体层的堆叠。 在形成HFET期间，在与HFET相邻的堆叠中形成肖特基二极管。 HFET和肖特基二极管同时形成，形成HFET的栅极的一层金属的一部分定位成与具有低带隙（例如小于0.8eV）的堆叠层接触，以提供 肖特基二极管的导通电压小于1.8伏。 肖特基二极管通过栅极电路连接到HFET的栅极接触，以补偿栅极电路中随着温度变化的电流负载的变化。

公开(公告)号：US06459344B1

公开(公告)日：2002-10-01

申请号：US09810681

申请日：2001-03-19

申请人： Anthony M. Pavio ,  Jenn-Hwa Huang ,  Wang-Chang Gu

发明人： Anthony M. Pavio ,  Jenn-Hwa Huang ,  Wang-Chang Gu

IPC分类号： H01P110

CPC分类号： H01H1/0036 ,  H01H19/00

摘要： A microelectromechanical system (MEMS) switch assembly (10) and a method of forming the MEMBS switch assembly (10) is provided that includes a switching member (12) having a first portion (34) that is at least partially formed with a first material having a first dielectric constant and a second portion (36) that is at least partially formed with a second material having a second dielectric constant. Furthermore, the switching member (12) further includes a first lead (14) spaced apart from a second lead (16) for contacting the switching member (12). In operation, the switching member (12) is configured for movement such that the first portion (34) and second portion (36) of the switching member (12) can provide variable electrical connections between the first lead (14) and second lead (16).

公开(公告)号：US06362018B1

公开(公告)日：2002-03-26

申请号：US09496930

申请日：2000-02-02

申请人： Ji-Hai Xu ,  Jenn-Hwa Huang ,  John Michael Parsey, Jr.

发明人： Ji-Hai Xu ,  Jenn-Hwa Huang ,  John Michael Parsey, Jr.

IPC分类号： H01L2100

CPC分类号： H01H59/0009 ,  H01G5/16

摘要： A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

摘要翻译： 具有可变电容的微机电系统装置在整个动态范围内是可控的，并且不受现有技术中常见的“卡扣效应”的制约。 该装置具有静电驱动器（120），其具有与可变电容（126）的第二驱动电容器串联的具有固定电容的驱动电容器（121）。 通过向静电驱动器（120）施加致动电压电位来控制MEMS可变电容器（130）。 静电驱动器（120）和MEMS可变电容器（130）集成在单个单片器件中。

公开(公告)号：US06156611A

公开(公告)日：2000-12-05

申请号：US119550

申请日：1998-07-20

申请人： Ellen Lan ,  Jenn-Hwa Huang ,  Kurt Eisenbeiser ,  Yang Wang

发明人： Ellen Lan ,  Jenn-Hwa Huang ,  Kurt Eisenbeiser ,  Yang Wang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66522 ,  H01L29/7827

摘要： A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

摘要翻译： 通过将接触层蚀刻到化合物半导体衬底上的漂移层中以形成多个台面来制造垂直FET，每个台面具有上表面，并且每个相邻的一对台面在其间限定具有侧壁和底部的沟槽。 导电层被共形沉积在多个台面和沟槽上并且各向异性地蚀刻以在沟槽的侧壁上形成接触，并且将沉积源触点放置在台面的上表面上以及在衬底的背面上的漏极接触。

公开(公告)号：US5880029A

公开(公告)日：1999-03-09

申请号：US775054

申请日：1996-12-27

申请人： Kurt Eisenbeiser ,  Jenn-Hwa Huang

发明人： Kurt Eisenbeiser ,  Jenn-Hwa Huang

IPC分类号： H01L21/316 ,  H01L21/318

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/3185

摘要： A method of passivating semiconductor devices including the steps of providing a semiconductor device having a surface of semiconductor material to be passivated, exposing the surface of semiconductor material to deep ultra-violet (DUV) radiation in an ambiance including oxygen so as to form a layer of oxide on the surface of semiconductor material, and forming a layer of passivation material on the layer of oxide. The DUV oxide forms a different interface with the semiconductor material which significantly improves operating characteristics of the semiconductor device.

摘要翻译： 一种钝化半导体器件的方法，包括以下步骤：提供具有要钝化的半导体材料表面的半导体器件，将半导体材料的表面暴露于包含氧的环境中的深紫外（DUV）辐射，以形成层 的半导体材料表面上的氧化物，并且在氧化物层上形成钝化材料层。 DUV氧化物与半导体材料形成不同的界面，这显着地改善了半导体器件的工作特性。

公开(公告)号：US5733827A

公开(公告)日：1998-03-31

申请号：US557405

申请日：1995-11-13

申请人： Saied N. Tehrani ,  Mark Durlam ,  Marino J. Martinez ,  Jenn-Hwa Huang ,  Ernie Schirmann

发明人： Saied N. Tehrani ,  Mark Durlam ,  Marino J. Martinez ,  Jenn-Hwa Huang ,  Ernie Schirmann

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L23/485 ,  H01L21/28 ,  H01L21/337

CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L23/485 ,  H01L2924/0002

摘要： A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

摘要翻译： 制造具有钝化表面的半导体器件的方法包括提供第一帽和蚀刻停止层以及其上具有接触层的第二帽和蚀刻停止层，以限定电极间表面积。 相对于彼此可选择性地蚀刻的第一层和绝缘层沉积在接触层和电极间表面区域上。 绝缘层和第一层被单独蚀刻以限定电极接触面积并暴露电极间表面积。 选择性地除去残留在接触区域中的第一蚀刻停止层和盖层的部分，并且在与绝缘层邻接接合的接触区域中形成金属接触，以密封电极间表面积。

公开(公告)号：US09153448B2

公开(公告)日：2015-10-06

申请号：US14601804

申请日：2015-01-21

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L21/285 ,  H01L21/311 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/10 ,  H01L29/812 ,  H01L29/20

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

公开(公告)号：US20130341678A1

公开(公告)日：2013-12-26

申请号：US13533610

申请日：2012-06-26

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L29/812 ,  H01L29/778 ,  H01L21/311

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。