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15 条记录 (耗时 0.018 秒)

    Logic structure and circuit for fast carry
    1.
    发明授权
    Logic structure and circuit for fast carry 失效
    逻辑结构和电路快速携带

    公开(公告)号：US5295090A

    公开(公告)日：1994-03-15

    申请号：US66674

    申请日：1993-05-24

    申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

    发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

    IPC分类号： G06F7/50 ,  G06F7/506

    CPC分类号： G06F7/506

    摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

    摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

    Programmable connector for programmable logic device
    2.
    发明授权
    Programmable connector for programmable logic device 失效
    可编程逻辑器件的可编程连接器

    公开(公告)号：US5140193A

    公开(公告)日：1992-08-18

    申请号：US499759

    申请日：1990-03-27

    申请人： Ross H. Freeman, deceased ,  Khue Duong ,  Hung-Cheng Hsieh ,  Charles R. Erickson ,  William S. Carter

    发明人： Ross H. Freeman, deceased ,  Khue Duong ,  Hung-Cheng Hsieh ,  Charles R. Erickson ,  William S. Carter

    IPC分类号： G06F3/00 ,  H01L21/82 ,  H03K19/173

    CPC分类号： H03K19/1736

    摘要： A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.

    Logic structure and circuit for fast carry
    3.
    发明授权
    Logic structure and circuit for fast carry 失效
    逻辑结构和电路快速携带

    公开(公告)号：US5267187A

    公开(公告)日：1993-11-30

    申请号：US944002

    申请日：1992-09-11

    申请人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

    发明人： Hung-Cheng Hsieh ,  William S. Carter ,  Charles S. Erickson ,  Edmond Y. Cheung

    IPC分类号： G06F7/50 ,  G06F7/57

    CPC分类号： G06F7/57 ,  G06F7/503 ,  G06F7/5057 ,  G06F7/506

    摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.

    摘要翻译： 使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。 当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。 本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。 本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当 这些位是相等的。

    Buffered routing element for a user programmable logic device
    4.
    发明授权
    Buffered routing element for a user programmable logic device 失效
    用于可编程逻辑器件的缓冲路由元件

    公开(公告)号：US4855619A

    公开(公告)日：1989-08-08

    申请号：US121963

    申请日：1987-11-17

    申请人： Hung-Cheng Hsieh ,  William S. Carter

    发明人： Hung-Cheng Hsieh ,  William S. Carter

    IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/177

    CPC分类号： H03K19/00361 ,  H03K19/018557 ,  H03K19/17712

    摘要： A programmable interconnect for programmably connecting transmission lines which are part of a configurable logic array is combined with a buffer at locations within the logic array where a signal will travel from a low capacitance line to a higher capacitance line. Use of a buffer in this arrangement allows for programmable interconnects controlling the configuration of the logic array to be smaller; consuming less power and providing for faster rise and fall of an output signal even when propagating through a long series of programmable interconnects. Several arrangements for programmably controlling the interconnect are taught. Also taught is a means of achieving a very wide AND gate without the need for cascading smaller devices.

    摘要翻译： 作为可配置逻辑阵列的一部分的可编程连接传输线的可编程互连与在逻辑阵列内的逻辑阵列中的缓冲器组合，其中信号将从低电容线行进到较高电容线。 在这种布置中使用缓冲器允许控制逻辑阵列的配置的可编程互连更小; 消耗较少的功率，并且即使在通过长串可编程互连传播时也能提供更快的输出信号上升和下降。 教导了可编程控制互连的几种布置。 还教导了实现非常宽的AND门的手段，而不需要级联较小的器件。

    5-Transistor memory cell which can be reliably read and written
    5.
    发明授权
    5-Transistor memory cell which can be reliably read and written 失效
    5晶体管存储单元可以可靠地读写

    公开(公告)号：US4750155A

    公开(公告)日：1988-06-07

    申请号：US777670

    申请日：1985-09-19

    申请人： Hung-Cheng Hsieh

    发明人： Hung-Cheng Hsieh

    IPC分类号： G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C7/12 ,  G11C11/41 ,  G11C11/412 ,  G11C7/20 ,  G11C8/08

    摘要： A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to read. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation.

    摘要翻译： 可以从单个数据线可靠地读取和写入的五晶体管存储单元。 电池包括两个反相器和一个传输晶体管。 单元读/写电路包括地址供应电压源，其在写入期间保持在第一电平，并且在读取期间保持在第二电平以减少读取干扰。 存储单元读取电路包括用于在读取之前预充电单元数据线的电路。 即使在读取操作期间，存储单元的状态在输出节点处连续可用以控制其它电路。

    Three-state bidirectional buffer
    6.
    发明授权
    Three-state bidirectional buffer 失效
    三态双向缓冲区

    公开(公告)号：US4835418A

    公开(公告)日：1989-05-30

    申请号：US121542

    申请日：1987-11-17

    申请人： Hung-Cheng Hsieh

    发明人： Hung-Cheng Hsieh

    IPC分类号： H03K5/02 ,  H03K19/094

    CPC分类号： H03K5/026 ,  H03K19/09429

    摘要： A bidirectional buffer having a high impedance state is provided. This buffer is used for amplifying a signal as it is passed from one transmission line to another when it is desirable to select which direction the signal will flow. A switching circuit controls which transmission line is connected to the input terminal of the buffer and which is connected to the output terminal. A high impedance state is also provided for disconnecting the two transmission lines. Two memory cells control the direction of signal flow and the high impedance state.

    摘要翻译： 提供具有高阻抗状态的双向缓冲器。 当希望选择信号将流向哪个方向时，该缓冲器用于将信号从一条传输线路传递到另一条传输线路时放大信号。 开关电路控制哪个传输线连接到缓冲器的输入端并连接到输出端。 还提供了用于断开两条传输线路的高阻抗状态。 两个存储单元控制信号流动的方向和高阻抗状态。

    Circuit for selecting a bit in a look-up table
    7.
    发明授权
    Circuit for selecting a bit in a look-up table 失效
    用于在查找表中选择位的电路

    公开(公告)号：US5488316A

    公开(公告)日：1996-01-30

    申请号：US429434

    申请日：1995-04-26

    申请人： Ross H. Freeman ,  Hung-Cheng Hsieh

    发明人： Ross H. Freeman ,  Hung-Cheng Hsieh

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1736

    摘要： This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

    摘要翻译： 本发明提供了具有逻辑功能的可配置逻辑阵列的附加电路，逻辑功能通过加载存储器单元来编程，这导致逻辑阵列产生期望的功能。 使用附加电路，存储器单元也可以用作在操作期间由逻辑阵列的其他部分访问的存储器。

    TTL/CMOS compatible input buffer
    9.
    发明授权
    TTL/CMOS compatible input buffer 失效
    TTL / CMOS兼容输入缓冲器

    公开(公告)号：US4820937A

    公开(公告)日：1989-04-11

    申请号：US778344

    申请日：1985-09-19

    申请人： Hung-Cheng Hsieh

    发明人： Hung-Cheng Hsieh

    IPC分类号： H03K3/3565 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/094 ,  H03K19/092

    CPC分类号： H03K19/0948 ,  H03K19/018521 ,  H03K3/3565

    摘要： A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysteresis to improve the noise immunity of the system. The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As a result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.

    摘要翻译： TTL / CMOS兼容输入缓冲器包括输入反相器和参考电压发生器。 在TTL模式中，参考电压发生器向逆变器中的P沟道晶体管的源极提供参考电压，其具有强制输入反相器的触发点呈现预选值的幅度。 通常，预选值被选择为1.4伏，以便最大化输入噪声容限。 第二级输入反相器引入滞后，以提高系统的抗噪声能力。 参考电压发生器包括连接到分压器网络的运算放大器。 在CMOS模式下，参考电压发生器被禁止，并且与输入逆变器提供等于电源电压的电压。 结果，输入反相器的触发点高于1.4伏，这提供了更大的输入噪声容限。 分压器网络和运算放大器掉电，不会消耗直流电源。