公开(公告)号：US08994023B2

公开(公告)日：2015-03-31

申请号：US13115088

申请日：2011-05-24

申请人： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

发明人： Hye-Young Ryu ,  Woo-Geun Lee ,  Young-Joo Choi ,  Kyoung-Jae Chung ,  Jin-Won Lee ,  Seung-Ha Choi ,  Hee-Jun Byeon ,  Pil-Sang Yun

IPC分类号： H01L47/00 ,  H01L29/10 ,  H01L29/04 ,  H01L29/15 ,  H01L27/12

CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

摘要： A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

摘要翻译： 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

公开(公告)号：US08598583B2

公开(公告)日：2013-12-03

申请号：US13092882

申请日：2011-04-22

申请人： Hye-Young Ryu ,  Jin-Won Lee ,  Woo-Geun Lee ,  Hee-Jun Byeon ,  Xun Zhu

发明人： Hye-Young Ryu ,  Jin-Won Lee ,  Woo-Geun Lee ,  Hee-Jun Byeon ,  Xun Zhu

IPC分类号： H01L29/786

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/3272 ,  H01L51/5253 ,  H01L2227/323

摘要： A thin film transistor panel includes a substrate, a light blocking layer on the substrate, a first protective film on the light blocking layer, a first electrode and a second electrode on the first protective film, an oxide semiconductor layer on a portion of the first protective film exposed between the first electrode and the second electrode, an insulating layer, a third electrode overlapping with the oxide semiconductor layer and on the insulating layer, and a fourth electrode on the insulating layer. The light blocking layer includes first sidewalls, and the first protective film includes second sidewalls. The first and the second sidewalls are disposed along substantially the same line.

公开(公告)号：US08866137B2

公开(公告)日：2014-10-21

申请号：US13365704

申请日：2012-02-03

申请人： Jin-Won Lee ,  Woo Geun Lee ,  Kap Soo Yoon ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Hee-Jun Byeon ,  Ji-Soo Oh

发明人： Jin-Won Lee ,  Woo Geun Lee ,  Kap Soo Yoon ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Hee-Jun Byeon ,  Ji-Soo Oh

IPC分类号： H01L29/12 ,  H01L27/12 ,  H01L29/417

CPC分类号： H01L27/1225 ,  H01L29/41733

摘要： A thin film transistor array panel includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a first electrode and an oxide semiconductor disposed directly on the gate insulating layer; a source electrode and a drain electrode formed on the oxide semiconductor; a passivation layer disposed on the first electrode, the source electrode, and the drain electrode; and a second electrode disposed on the passivation layer.

摘要翻译： 薄膜晶体管阵列面板包括：设置在绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 直接设置在栅极绝缘层上的第一电极和氧化物半导体; 形成在所述氧化物半导体上的源电极和漏电极; 设置在所述第一电极，所述源电极和所述漏电极上的钝化层; 以及设置在钝化层上的第二电极。

公开(公告)号：US20110284852A1

公开(公告)日：2011-11-24

申请号：US13049783

申请日：2011-03-16

申请人： Ki-Won KIM ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

发明人： Ki-Won KIM ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

摘要： A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

摘要翻译： 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US08772897B2

公开(公告)日：2014-07-08

申请号：US13049783

申请日：2011-03-16

申请人： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

发明人： Ki-Won Kim ,  Kap-Soo Yoon ,  Woo-Geun Lee ,  Yeong-Keun Kwon ,  Hye-Young Ryu ,  Jin-Won Lee ,  Hyun-Jung Lee

IPC分类号： H01L27/146

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78645 ,  H01L29/78648

摘要： A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

摘要翻译： 薄膜晶体管包括半导体图案，第一栅电极，源电极，漏电极和第二栅电极。 半导体图案形成在基板上。 第一导电层具有包括与半导体图案电绝缘的第一栅电极的图案。 第二导电层具有图案，其包括电连接到半导体图案的源电极，与源电极间隔开的漏电极和与第一栅电极电连接的第二栅电极。 第二栅电极与半导体图案，源电极和漏电极电绝缘。

公开(公告)号：US09178024B2

公开(公告)日：2015-11-03

申请号：US13464613

申请日：2012-05-04

申请人： Ki-Won Kim ,  Kap Soo Yoon ,  Woo Geun Lee ,  Jin-Won Lee ,  Se-Myung Kwon ,  Jung Ouck Ahn ,  Si Jin Kim

发明人： Ki-Won Kim ,  Kap Soo Yoon ,  Woo Geun Lee ,  Jin-Won Lee ,  Se-Myung Kwon ,  Jung Ouck Ahn ,  Si Jin Kim

IPC分类号： H01L21/00 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/66765 ,  H01L29/78696

摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.

摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成从栅极线突出的栅极线和栅电极; 在栅极线和栅电极上形成栅极绝缘层; 在栅极绝缘层上依次沉积半导体材料和金属材料; 使用第一掩模对所述半导体材料和所述金属材料进行第一蚀刻操作以形成半导体层和金属层，所述金属层包括数据线，源电极和漏电极，其中所述漏电极突出 数据线，源电极和漏电极具有整体形状; 以及使用第二掩模对所述金属层进行第二蚀刻操作以分割所述源电极和所述漏电极。

公开(公告)号：US08950036B2

公开(公告)日：2015-02-10

申请号：US12965239

申请日：2010-12-10

申请人： Wataru Kaihotsu ,  Jeong-Hyun Shim ,  Jin-Won Lee

发明人： Wataru Kaihotsu ,  Jeong-Hyun Shim ,  Jin-Won Lee

IPC分类号： H04N5/225

CPC分类号： H04N5/2254

摘要： A dust remover according to the present disclosure forms an air flow in a space formed between a charge-coupled device and a shutter unit, and removes dust on a surface of the charge-coupled device, the dust remover comprising an air injector having a plurality of air injecting holes; an air discharger which is installed on a surface facing the air injector, and has at least one air discharging hole which is smaller than the air injecting hole; and an exhausting dust collecting filter which is installed in the air discharger, and collects dust in the air being discharged.

摘要翻译： 根据本公开的除尘器在形成在电荷耦合器件和快门单元之间的空间中形成空气流，并去除电荷耦合器件表面上的灰尘，除尘器包括具有多个 空气注入孔; 安装在面向空气喷射器的表面上的排气器，并且具有比空气喷射孔小的至少一个排气孔; 以及安装在排气器中的排出的集尘过滤器，并且收集被排出的空气中的灰尘。

公开(公告)号：US08735110B2

公开(公告)日：2014-05-27

申请号：US13642127

申请日：2011-03-07

申请人： Jin-Won Lee ,  Sun-Hee Lee ,  Eun-Young Jeon

发明人： Jin-Won Lee ,  Sun-Hee Lee ,  Eun-Young Jeon

IPC分类号： C12P7/64 ,  C12N1/12

CPC分类号： C12N15/52 ,  C12N9/1029 ,  C12N9/16 ,  C12N9/93 ,  C12P7/6409 ,  C12P7/6463 ,  C12Y203/01039 ,  C12Y301/02014 ,  C12Y604/01002

摘要： Disclosed are novel Pseudomonas aeruginosa strains capable of producing in high yield and preparation methods thereof. The strains anchor an expression vector carrying either or both of a nucleotide sequence coding for acetyl-CoA carboxylase carboxytransferase subunit alpha of Pseudomonas aeruginosa and a nucleotide sequence coding for malonyl-CoA-[acyl-carrier-protein] transacylase of Pseudomonas aeruginosa, and/or a nucleotide sequence coding for acyl-acyl carrier protein thioesterase of Streptococcus pyogenes. The recombinant Pseudomonas aeruginosa strains are genetically stable and have high lipid or fatty acid contents, thus being applicable to the mass production of fatty acids.

摘要翻译： 公开了能够高产量生产的新型铜绿假单胞菌菌株及其制备方法。 菌株锚定携带编码铜绿假单胞菌的乙酰辅酶A羧化酶羧基转移酶亚基α的核苷酸序列的一个或两个的表达载体和编码铜绿假单胞菌的丙二酰-CoA- [酰基 - 载体 - 蛋白]转酰酶的核苷酸序列和/ 或编码化脓性链球菌的酰基酰基载体蛋白硫酯酶的核苷酸序列。 重组铜绿假单胞菌在遗传上具有稳定性，脂质含量高，脂肪酸含量高，适用于大量生产脂肪酸。

公开(公告)号：US08471819B2

公开(公告)日：2013-06-25

申请号：US12435369

申请日：2009-05-04

申请人： Hyaung-Sic You ,  Jin-Won Lee

发明人： Hyaung-Sic You ,  Jin-Won Lee

IPC分类号： G09G5/00

CPC分类号： G06F3/0219 ,  H04M1/23 ,  H04M2250/22

摘要： A mobile communications terminal and a method for preventing an input error of a key input unit are provided. The mobile communications terminal includes a touch sensor unit for sensing a key that is input by touching a keypad region in order to output a key input signal corresponding to the key and a controller adapted to determine a key input according to either a priority between multiple keys from which key signals are received or whether a received key signal was generated inadvertently.

公开(公告)号：US08287196B2

公开(公告)日：2012-10-16

申请号：US12969227

申请日：2010-12-15

申请人： Hae-In Chung ,  Jin-Won Lee

发明人： Hae-In Chung ,  Jin-Won Lee

IPC分类号： G03B9/08

CPC分类号： G03B9/32

摘要： A focal plane shutter having a front film and a back film which expose a charge-coupled device to light as they move back and forth between a cover plate and a base plate, between a charging position and a discharging position at a certain time interval. The focal plane shutter includes at least one lever member which is connected to the front film and/or back film, and which amplifies an impact force generated during a charging and a discharging movement of the front film and/or back film using a lever action. An elevating member slides in a direction parallel with the movement of the front film and/or back film by the impact force amplified in the lever member. An impact absorbing unit regulates the sliding movement of the elevating member to absorb impact energy generated by the movement and stop of the front film and/or back film.

摘要翻译： 具有前膜和背膜的焦平面快门，当电荷耦合器件在盖板和基板之间来回移动时，以一定的时间间隔在充电位置和放电位置之间曝光。 焦平面快门包括至少一个杠杆构件，其连接到前膜和/或后膜，并且利用杠杆动作放大在前膜和/或后膜的充电和排出运动期间产生的冲击力 。 升降构件通过在杆构件中放大的冲击力沿与前膜和/或后膜的移动平行的方向滑动。 冲击吸收单元调节升降构件的滑动运动，以吸收由前膜和/或后膜的运动和停止产生的冲击能。