公开(公告)号：US20080237566A1

公开(公告)日：2008-10-02

申请号：US11905244

申请日：2007-09-28

申请人： Hyeong-Geun AN ,  Hideki HORII ,  Jong-Chan SHIN ,  Dong-Ho AHN ,  Jun-Soo BAE ,  Jeong-Hee PARK

发明人： Hyeong-Geun AN ,  Hideki HORII ,  Jong-Chan SHIN ,  Dong-Ho AHN ,  Jun-Soo BAE ,  Jeong-Hee PARK

IPC分类号： H01L47/00

CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane

摘要翻译： 提供了一种相变存储器件及其制造方法。 具有第一表面的第一电极设置在基板上。 具有与第一表面不同的第二表面的第二电极在基板上。 第二电极可以与第一电极间隔开。 可以对应于第一电极形成第三电极。 可以对应于第二电极形成第四电极。 可以在第一表面和第三电极之间插入第一相变图案。 可以在第二表面和第四电极之间插入第二相变图案。 第一和第二相变图案的上表面可以在同一平面上

公开(公告)号：US20070190683A1

公开(公告)日：2007-08-16

申请号：US11674580

申请日：2007-02-13

申请人： Jun-Soo BAE ,  Hideki HORII ,  Ji-Hye YI ,  Young-Soo LIM

发明人： Jun-Soo BAE ,  Hideki HORII ,  Ji-Hye YI ,  Young-Soo LIM

IPC分类号： H01L21/00

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.

摘要翻译： 本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。 首先通过（i）在下电极上形成包括硫族化物的相变层来形成堆叠复合体，（ii）形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层 可变层，和（iii）形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。 然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。 然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层，以分别形成蚀刻停止图案和相变图案。

公开(公告)号：US20100103726A1

公开(公告)日：2010-04-29

申请号：US12652842

申请日：2010-01-06

申请人： Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

发明人： Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

摘要： A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

摘要翻译： 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20160155934A1

公开(公告)日：2016-06-02

申请号：US14887506

申请日：2015-10-20

申请人： Kyu-Man HWANG ,  Shi-Jung KIM ,  Mi-Lim PARK ,  Jun-Soo BAE ,  Seung-Woo LEE

发明人： Kyu-Man HWANG ,  Shi-Jung KIM ,  Mi-Lim PARK ,  Jun-Soo BAE ,  Seung-Woo LEE

IPC分类号： H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC分类号： H01L43/08 ,  H01L43/12

摘要： Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.

摘要翻译： 磁性随机存取存储器（MRAM）器件及其制造方法包括在衬底上的至少一个第一磁性材料图案，至少一个第一磁性材料图案上的至少一个第二磁性材料图案，以及至少一个隧道 所述至少一个第一磁性材料图案和所述至少一个第二磁性材料图案之间的阻挡层图案。 所述至少一个第一磁性材料图案的顶表面的宽度可以小于所述至少一个第二磁性材料图案的底表面的宽度。

公开(公告)号：US20100085799A1

公开(公告)日：2010-04-08

申请号：US12632018

申请日：2009-12-07

申请人： Woo-Yeong CHO ,  Ki-Sung KIM ,  Du-Eung KIM ,  Kwang-Jin LEE ,  Jun-Soo BAE

发明人： Woo-Yeong CHO ,  Ki-Sung KIM ,  Du-Eung KIM ,  Kwang-Jin LEE ,  Jun-Soo BAE

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2211/5634

摘要： Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.

摘要翻译： 公开了一种驱动多电平可变电阻存储器件的方法。 驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定的电阻窗，预期电阻 窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少的量的写入电流，以便改变可变电阻存储单元的电阻。

公开(公告)号：US20070041243A1

公开(公告)日：2007-02-22

申请号：US11465075

申请日：2006-08-16

申请人： Jun-Soo BAE ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Kyung-Tae NAM

发明人： Jun-Soo BAE ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Kyung-Tae NAM

IPC分类号： G11C11/00

CPC分类号： G11C11/15 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3281 ,  H01F41/302 ,  H01L43/08

摘要： There is provided a magnetic memory device and a method of forming the same. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions.

摘要翻译： 提供了一种磁存储器件及其形成方法。 磁存储器件在衬底上包括不变的钉扎图案和可变的钉扎图案。 在不变的钉扎图案和可变钉扎图案之间插入隧道势垒图案，并且钉扎图案介于不变钉扎图案和隧道屏障图案之间。 在隧道势垒图案和可变钉扎图案之间插入无存储图案，并且在存储空闲图案和可变钉扎图案之间插入无引导图案。 在存储和无引导模式之间插入一个自由的反转模式。 自由反转图案反转无存储图案的磁化方向和反向自由图案的磁化方向。

公开(公告)号：US20070041125A1

公开(公告)日：2007-02-22

申请号：US11552085

申请日：2006-10-23

申请人： Young-Ki HA ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Jun-Soo BAE ,  In-Gyu BAEK

发明人： Young-Ki HA ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Jun-Soo BAE ,  In-Gyu BAEK

IPC分类号： G11B5/17

CPC分类号： H01L43/12 ,  H01L43/08

摘要： There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

摘要翻译： 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

公开(公告)号：US20120273741A1

公开(公告)日：2012-11-01

申请号：US13443132

申请日：2012-04-10

申请人： Kyu-Man HWANG ,  Jun-Soo BAE ,  Sung-Un KWON ,  Kwang-Ho PARK

发明人： Kyu-Man HWANG ,  Jun-Soo BAE ,  Sung-Un KWON ,  Kwang-Ho PARK

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1683

摘要： A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.

摘要翻译： 一种制造相变存储器件的方法包括：形成下电极层图案和覆盖下电极层图案的绝缘夹层，在绝缘中间层中形成第一开口以露出下电极层图案，在其上形成氧化层图案 通过部分地除去氧化物层和下部电极层图案，形成绝缘层，在第一开口的侧壁和下部电极的下方形成氧化物层图案，形成绝缘层，填充第一开口的剩余部分，通过湿蚀刻工艺去除氧化物层图案 以形成第二开口，并且在下电极上形成相变材料图案，使得相变材料图案填充第二开口。

公开(公告)号：US20080153179A1

公开(公告)日：2008-06-26

申请号：US12073098

申请日：2008-02-29

申请人： Se-Chung OH ,  Jang-Eun LEE ,  Jun-Soo BAE ,  Hyun-Jo KIM ,  Kyung-Tae NAM ,  Young-Ki HA

发明人： Se-Chung OH ,  Jang-Eun LEE ,  Jun-Soo BAE ,  Hyun-Jo KIM ,  Kyung-Tae NAM ,  Young-Ki HA

IPC分类号： H01L21/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

摘要： Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

公开(公告)号：US20070166870A1

公开(公告)日：2007-07-19

申请号：US11623890

申请日：2007-01-17

申请人： Young-Soo LIM ,  Jae-Seung HWANG ,  Hyun-Chul KIM ,  Jun-Soo BAE

发明人： Young-Soo LIM ,  Jae-Seung HWANG ,  Hyun-Chul KIM ,  Jun-Soo BAE

IPC分类号： H01L21/00

CPC分类号： H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

摘要： In one embodiment, a phase-changeable structure can be formed by forming a phase-changeable layer on the lower electrode, forming a conductive layer on the phase-changeable layer, etching the conductive layer using a first etching material to form an upper electrode and etching the phase-changeable layer using a second etching material to form a phase-changeable pattern. The first etching material can include a first component containing fluorine. The second etching material does not contain chlorine.

摘要翻译： 在一个实施例中，可以通过在下电极上形成相变层，在相变层上形成导电层，使用第一蚀刻材料蚀刻导电层以形成上电极和 使用第二蚀刻材料蚀刻相变层以形成相变图案。 第一蚀刻材料可以包括含氟的第一成分。 第二蚀刻材料不含氯。