公开(公告)号：US20070111532A1

公开(公告)日：2007-05-17

申请号：US11600224

申请日：2006-11-16

申请人： Hyo-san Lee ,  Hyung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Hyo-san Lee ,  Hyung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/00 ,  H01L21/302

CPC分类号： H01L29/78696 ,  C09K13/08 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/10826 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

摘要： A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.

公开(公告)号：US07176041B2

公开(公告)日：2007-02-13

申请号：US10976161

申请日：2004-10-29

申请人： Hyo-san Lee ,  Hyung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Hyo-san Lee ,  Hyung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/78696 ,  C09K13/08 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/10826 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

摘要： A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.

摘要翻译： 湿蚀刻组合物可以包括：过乙酸（PAA）; 和氟化酸; 组合物中PAA的相对量足以确保与（N掺杂SiGe）的蚀刻速率基本相同的（P掺杂SiGe）:( P掺杂Si）的蚀刻速率： （N掺杂Si）。 这种湿蚀刻组合物在下文中称为基于PAA的蚀刻剂，并且可以用于制造例如CMOS MBCFET，电容器的电极等

公开(公告)号：US20050169096A1

公开(公告)日：2005-08-04

申请号：US10976161

申请日：2004-10-29

申请人： Hyo-san Lee ,  Hyung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Hyo-san Lee ,  Hyung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/308 ,  C09K13/08 ,  C23F1/24 ,  G11C8/02 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786

CPC分类号： H01L29/78696 ,  C09K13/08 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/10826 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

摘要： A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.

摘要翻译： 湿蚀刻组合物可以包括：过乙酸（PAA）; 和氟化酸; 组合物中PAA的相对量足以确保与（N掺杂SiGe）的蚀刻速率基本相同的（P掺杂SiGe）:( P掺杂Si）的蚀刻速率： （N掺杂Si）。 这种湿蚀刻组合物在下文中称为基于PAA的蚀刻剂，并且可以用于制造例如CMOS MBCFET，电容器的电极等

公开(公告)号：US20060246666A1

公开(公告)日：2006-11-02

申请号：US11410837

申请日：2006-04-26

申请人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

摘要翻译： 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

公开(公告)号：US07709277B2

公开(公告)日：2010-05-04

申请号：US11600224

申请日：2006-11-16

申请人： Hyo-san Lee ,  Hung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Hyo-san Lee ,  Hung-ho Ko ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/00 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L29/78696 ,  C09K13/08 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/10826 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

摘要： A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.

摘要翻译： 湿蚀刻组合物可以包括：过乙酸（PAA）; 和氟化酸; 组合物中PAA的相对量足以确保与（N掺杂SiGe）的蚀刻速率基本相同的（P掺杂SiGe）:( P掺杂Si）的蚀刻速率： （N掺杂Si）。 这种湿蚀刻组合物在下文中称为基于PAA的蚀刻剂，并且可以用于制造例如CMOS MBCFET，电容器的电极等

公开(公告)号：US20060228890A1

公开(公告)日：2006-10-12

申请号：US11402028

申请日：2006-04-12

申请人： Hyo-san Lee ,  Sang-yong Kim ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim ,  Im-soo Park ,  Kui-jong Baik ,  Woong Han ,  Jung-hun Lim ,  Sang-won Lee ,  Sung-bae Kim ,  Hyun-tak Kim

发明人： Hyo-san Lee ,  Sang-yong Kim ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim ,  Im-soo Park ,  Kui-jong Baik ,  Woong Han ,  Jung-hun Lim ,  Sang-won Lee ,  Sung-bae Kim ,  Hyun-tak Kim

IPC分类号： C03C15/00 ,  H01L21/302 ,  B08B6/00 ,  C09K13/00

CPC分类号： H01L21/0206 ,  C09K13/08 ,  C23G1/10 ,  H01L21/02071

摘要： A cleaning solution includes acetic acid, an inorganic acid, a fluoride compound, and deionized water, and may further include a corrosion inhibitor, a chelating agent, or a combination thereof. The cleaning solution may be used in the formation of a metal pattern in which a metal film including ruthenium is formed on a surface of a substrate, and a portion of the metal film is dry-etched to form a metal film pattern. After dry-etching, the metal film pattern is cleaned with the cleaning solution to remove an etching by-product layer around the metal film pattern. The cleaning solution may also be used to remove an etching by-product layer around an oxide film pattern prior to dry-etching of the metal film.

摘要翻译： 清洁溶液包括乙酸，无机酸，氟化物和去离子水，并且还可以包括腐蚀抑制剂，螯合剂或其组合。 清洗液可用于形成在基材表面上形成包含钌的金属膜的金属图案，并且将金属膜的一部分干蚀刻以形成金属膜图案。 在干蚀刻之后，用清洁溶液清洗金属膜图案以除去金属膜图案周围的蚀刻副产物层。 在干蚀刻金属膜之前，还可以使用清洁溶液去除氧化膜图案周围的蚀刻副产物层。

公开(公告)号：US07459370B2

公开(公告)日：2008-12-02

申请号：US11546420

申请日：2006-10-12

申请人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

发明人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

IPC分类号： H01L21/20

CPC分类号： H01L28/90 ,  H01L21/0334 ,  H01L21/31144 ,  H01L27/10852

摘要： In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate. The method further includes selectively removing, including wet etching, the mold insulating film to expose a sidewall of at least one storage node electrode among the storage node electrodes covered by the capping film, and removing the capping film by dry etching to expose upper portions of the storage node electrodes.

摘要翻译： 一方面，提供一种制造半导体存储器件的方法，其包括在半导体衬底的第一和第二部分上形成模绝缘膜，其中所述模绝缘膜包括在所述第一部分上分开的多个存储节点电极孔 的半导体衬底。 该方法还包括分别在存储节点电极孔的内表面上形成多个存储节点电极，并且形成覆盖存储节点电极的封盖膜和位于第一部分上的模具绝缘膜的第一部分 半导体衬底，并且暴露位于半导体衬底的第二部分上方的模具绝缘膜的第二部分。 该方法还包括选择性地去除包括湿式蚀刻的模具绝缘膜，以暴露由覆盖膜覆盖的存储节点电极中的至少一个存储节点电极的侧壁，以及通过干蚀刻去除封盖膜以暴露 存储节点电极。

公开(公告)号：US20070082471A1

公开(公告)日：2007-04-12

申请号：US11546420

申请日：2006-10-12

申请人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

发明人： Dae-hyuk Kang ,  Jung-min Oh ,  Chang-ki Hong ,  Sang-jun Choi ,  Woo-gwan Shim

IPC分类号： H01L21/3205

CPC分类号： H01L28/90 ,  H01L21/0334 ,  H01L21/31144 ,  H01L27/10852

摘要： In one aspect, a method of fabricating a semiconductor memory device is provided which includes forming a mold insulating film over first and second portions of a semiconductor substrate, where the mold insulating film includes a plurality of storage node electrode holes spaced apart over the first portion of the semiconductor substrate. The method further includes forming a plurality of storage node electrodes on inner surfaces of the storage node electrode holes, respectively, and forming a capping film which covers the storage node electrodes and a first portion of the mold insulating film located over the first portion of the semiconductor substrate, and which exposes a second portion of the mold insulating film located over the second portion of the semiconductor substrate. The method further includes selectively removing, including wet etching, the mold insulating film to expose a sidewall of at least one storage node electrode among the storage node electrodes covered by the capping film, and removing the capping film by dry etching to expose upper portions of the storage node electrodes.

摘要翻译： 一方面，提供一种制造半导体存储器件的方法，其包括在半导体衬底的第一和第二部分上形成模绝缘膜，其中所述模绝缘膜包括在所述第一部分上分开的多个存储节点电极孔 的半导体衬底。 该方法还包括分别在存储节点电极孔的内表面上形成多个存储节点电极，并且形成覆盖存储节点电极的封盖膜和位于第一部分上的模具绝缘膜的第一部分 半导体衬底，并且暴露位于半导体衬底的第二部分上方的模具绝缘膜的第二部分。 该方法还包括选择性地去除包括湿式蚀刻的模具绝缘膜，以暴露由覆盖膜覆盖的存储节点电极中的至少一个存储节点电极的侧壁，以及通过干蚀刻去除封盖膜以暴露 存储节点电极。

公开(公告)号：US20130029490A1

公开(公告)日：2013-01-31

申请号：US13190378

申请日：2011-07-25

申请人： Kyeong Tae Lee ,  Sang Wook Kim ,  Daehee Weon ,  Sang-jun Choi ,  Sreekar Bhaviripudi ,  Jahyong Kuh

发明人： Kyeong Tae Lee ,  Sang Wook Kim ,  Daehee Weon ,  Sang-jun Choi ,  Sreekar Bhaviripudi ,  Jahyong Kuh

IPC分类号： H01L21/312

CPC分类号： H01L21/02 ,  H01L21/0273 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139

摘要： A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.

公开(公告)号：US07985961B2

公开(公告)日：2011-07-26

申请号：US12003133

申请日：2007-12-20

申请人： Sang-jun Choi ,  Jung-hyun Lee ,  Chang-soo Lee

发明人： Sang-jun Choi ,  Jung-hyun Lee ,  Chang-soo Lee

IPC分类号： H01L47/00

CPC分类号： H01L45/1226 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/142 ,  H01L45/144 ,  H01L45/1675

摘要： Example embodiments may provide resistive random access memory devices and/or methods of manufacturing resistive random access memory devices. Example embodiment resistive random access memory devices may include a switching device and/or a storage node connected to the switching device. The storage node may include a stack structure including a plurality of resistance change layers separated from one another and first and second electrodes each on a side wall of the stack structure. The resistance change layers may be connected to the first and the second electrodes in parallel and/or may have different switching voltages from each other.

摘要翻译： 示例性实施例可以提供电阻性随机存取存储器件和/或制造电阻随机存取存储器件的方法。 示例性实施例电阻随机存取存储器设备可以包括连接到交换设备的交换设备和/或存储节点。 存储节点可以包括堆叠结构，其包括彼此分离的多个电阻变化层以及每个在堆叠结构的侧壁上的第一和第二电极。 电阻变化层可以并联连接到第一和第二电极和/或可以具有彼此不同的开关电压。