公开(公告)号：US09343672B2

公开(公告)日：2016-05-17

申请号：US13442595

申请日：2012-04-09

申请人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

发明人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/1253 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

摘要翻译： 非易失性存储单元包括彼此分离并依次堆叠的第一和第二层间绝缘膜，穿过第一层间绝缘膜和第二层间绝缘膜的第一电极，沿着侧表面形成的电阻变化膜 并且平行于第一电极延伸，以及形成在第一层间绝缘膜和第二层间绝缘膜之间的第二电极。 第二电极包括由金属制成的导电膜和防止导电膜中包含的导电材料扩散的防扩散膜。

公开(公告)号：US20120313066A1

公开(公告)日：2012-12-13

申请号：US13442595

申请日：2012-04-09

申请人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

发明人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/1253 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

摘要翻译： 非易失性存储单元包括彼此分离并依次堆叠的第一和第二层间绝缘膜，穿过第一层间绝缘膜和第二层间绝缘膜的第一电极，沿着侧表面形成的电阻变化膜 并且平行于第一电极延伸，以及形成在第一层间绝缘膜和第二层间绝缘膜之间的第二电极。 第二电极包括由金属制成的导电膜和防止导电膜中包含的导电材料扩散的防扩散膜。

公开(公告)号：US08884262B2

公开(公告)日：2014-11-11

申请号：US13487570

申请日：2012-06-04

申请人： Hyun-Su Ju ,  Sun-Jung Kim ,  Soo-Doo Chae

发明人： Hyun-Su Ju ,  Sun-Jung Kim ,  Soo-Doo Chae

IPC分类号： H01L29/06 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.

摘要翻译： 提供了一种非易失性存储器件，其中在基底上形成下模制层; 在下模制层上形成第一水平互连; 上模塑层形成在第一水平互连上; 通过垂直地穿过上模制层，第一水平互连和下模制层而形成连接到基板的支柱。 所述支柱具有下部和上部，其中所述下部设置在与所述第一水平互连相同的高度上并具有第一宽度，并且所述上部设置在比所述第一水平互连更高的高度上，并且具有第二 宽度与第一宽度不同。

公开(公告)号：US20120305877A1

公开(公告)日：2012-12-06

申请号：US13487570

申请日：2012-06-04

申请人： Hyun-Su Ju ,  Sun-Jung Kim ,  Soo-Doo Chae

发明人： Hyun-Su Ju ,  Sun-Jung Kim ,  Soo-Doo Chae

IPC分类号： H01L47/00

CPC分类号： H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.

摘要翻译： 提供了一种非易失性存储器件，其中在基底上形成下模制层; 在下模制层上形成第一水平互连; 上模塑层形成在第一水平互连上; 通过垂直地穿过上模制层，第一水平互连和下模制层而形成连接到基板的支柱。 支柱具有下部和上部，其中下部设置在与第一水平互连相同的高度上并具有第一宽度，并且上部设置在比第一水平互连更高的高度上，并且具有第二 宽度与第一宽度不同。

公开(公告)号：US07994003B2

公开(公告)日：2011-08-09

申请号：US12382646

申请日：2009-03-20

申请人： Byong-Ju Kim ,  Sun-Jung Kim ,  Zong-Liang Huo ,  Jun-Kyu Yang ,  Seon-Ho Jo ,  Han-Mei Choi ,  Young-Sun Kim

发明人： Byong-Ju Kim ,  Sun-Jung Kim ,  Zong-Liang Huo ,  Jun-Kyu Yang ,  Seon-Ho Jo ,  Han-Mei Choi ,  Young-Sun Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/84 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

摘要： A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成电介质层，电介质层包括第一氧化铝层， 氧化硅层和第二氧化铝层，所述第二氧化铝层依次堆叠在所述电荷存储层上，并且在所述电介质层上形成栅电极，所述栅电极与所述电介质层的所述第二氧化铝层直接接触。

公开(公告)号：US20080090353A1

公开(公告)日：2008-04-17

申请号：US11859618

申请日：2007-09-21

申请人： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

发明人： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of manufacturing a non-volatie memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.

摘要翻译： 制造非挥发性记忆装置的方法包括在基板上形成隧道绝缘层，在隧道绝缘层上形成导电图案，在导电图案上形成下介电层，进行第一热处理工艺以密度较低 并且形成具有比第一经热处理的下电介质层上的下介电层的能带隙小的能带隙的中间电介质层。 该方法还包括形成上介电层，其包括与中间介电层上的下电介质层的材料基本相同的材料，执行第二热处理工艺以使中介电层和上电介质层致密并形成导电层 第二热处理的上介电层。

公开(公告)号：US20110198685A1

公开(公告)日：2011-08-18

申请号：US13095408

申请日：2011-04-27

申请人： Hyun-Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

发明人： Hyun-Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

摘要翻译： 提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

公开(公告)号：US07412982B2

公开(公告)日：2008-08-19

申请号：US11240554

申请日：2005-10-03

申请人： Sun-Jung Kim

发明人： Sun-Jung Kim

IPC分类号： B08B3/00 ,  B08B3/12 ,  B08B6/00

CPC分类号： H01L21/67051 ,  B08B3/12 ,  Y10S134/902 ,  Y10S438/906

摘要： A cleaning probe capable of providing uniform cleaning to an entire wafer while not damaging the edge portion of the wafer, and a megasonic cleaning apparatus having the cleaning probe are provided. The cleaning probe comprises a front portion located near the center of the wafer, a rear portion connected to a piezoelectric transducer, and a protrusion located between the rear portion and the front portion, located on an edge portion of the wafer, and having a larger cross section width than the front portion.

摘要翻译： 提供能够在不损坏晶片的边缘部分的同时对整个晶片提供均匀清洁的清洁探针，以及具有清洁探针的兆声波清洗装置。 清洁探针包括位于晶片中心附近的前部，连接到压电换能器的后部，以及位于晶片的边缘部分之间位于后部和前部之间的突起，并且具有较大的 横截面宽度大于前面部分。

公开(公告)号：US07964908B2

公开(公告)日：2011-06-21

申请号：US12111239

申请日：2008-04-29

申请人： Sun-Jung Kim ,  Young-Sun Kim ,  Se-Hoon Oh ,  Eun-Ha Lee ,  Young-Su Chung

发明人： Sun-Jung Kim ,  Young-Sun Kim ,  Se-Hoon Oh ,  Eun-Ha Lee ,  Young-Su Chung

IPC分类号： H01L29/792

CPC分类号： H01L29/42332 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

摘要： In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectric material, where an oxygen concentration of the dielectric material is the greater than an oxygen concentration of the nano regions. In another aspect, at least one of the dielectric layers includes a dielectric material and nano regions embedded in the dielectric material, where an atomic composition of the dielectric material is the same as the atomic composition of the nano regions, and a density of the dielectric material is the greater than a density of the nano regions.

摘要翻译： 在一个方面，存储单元包括位于电荷存储栅极结构内的多个电介质层。 电介质层中的至少一个包括包含氧的介电材料和包含在介电材料中的氧的纳米区域，其中电介质材料的氧浓度大于纳米区域的氧浓度。 另一方面，电介质层中的至少一个包括介电材料和嵌入电介质材料中的纳米区域，其中介电材料的原子组成与纳米区域的原子组成相同，并且电介质的密度 材料大于纳米区域的密度。

公开(公告)号：US20090239367A1

公开(公告)日：2009-09-24

申请号：US12382646

申请日：2009-03-20

申请人： Byong-Ju Kim ,  Sun-Jung Kim ,  Zong-Liang Huo ,  Jun-Kyu Yang ,  Seon-Ho Jo ,  Han-Mei Choi ,  Young-Sun Kim

发明人： Byong-Ju Kim ,  Sun-Jung Kim ,  Zong-Liang Huo ,  Jun-Kyu Yang ,  Seon-Ho Jo ,  Han-Mei Choi ,  Young-Sun Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31612 ,  H01L21/3162 ,  H01L21/84 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792

摘要： A method of fabricating a nonvolatile memory device includes forming a tunnel insulating layer on a semiconductor substrate, forming a charge storage layer on the tunnel insulating layer, forming a dielectric layer on the charge storage layer, the dielectric layer including a first aluminum oxide layer, a silicon oxide layer, and a second aluminum oxide layer sequentially stacked on the charge storage layer, and forming a gate electrode on the dielectric layer, the gate electrode directly contacting the second aluminum oxide layer of the dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道绝缘层，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成电介质层，电介质层包括第一氧化铝层， 氧化硅层和第二氧化铝层，所述第二氧化铝层依次堆叠在所述电荷存储层上，并且在所述电介质层上形成栅电极，所述栅电极与所述电介质层的所述第二氧化铝层直接接触。