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    Integrated circuit devices including low-resistivity conductive patterns in recessed regions
    1.
    发明授权
    Integrated circuit devices including low-resistivity conductive patterns in recessed regions 有权
    集成电路器件包括凹陷区域中的低电阻率导电图案

    公开(公告)号：US08294131B2

    公开(公告)日：2012-10-23

    申请号：US12826896

    申请日：2010-06-30

    申请人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    发明人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    IPC分类号： H01L29/02

    CPC分类号： H01L27/228 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/2454 ,  H01L27/2463

    摘要： An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.

    摘要翻译： 集成电路器件包括在半导体衬底上的器件隔离图案，以在其中限定有效区域。 有源区域包括其中的掺杂区域。 导电图案在有源区上延伸并与掺杂区电接触。 导电图案具有比掺杂区域更低的电阻率。 导电图案可以设置在具有低于有源区域的顶表面的底表面的凹陷区域中。 通道柱与掺杂区电接触并从远离衬底的方向从其延伸。 导电栅电极设置在通道柱的侧壁上，并且栅极电介质层设置在沟道柱的栅电极和侧壁之间。

    Method of fabricating vertical channel transistor
    2.
    发明授权
    Method of fabricating vertical channel transistor 有权
    制造垂直沟道晶体管的方法

    公开(公告)号：US08053316B2

    公开(公告)日：2011-11-08

    申请号：US12953785

    申请日：2010-11-24

    申请人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    发明人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10885 ,  H01L29/66666 ,  H01L29/7827

    摘要： A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; forming a buried bit line extending in the first horizontal direction on the substrate; and forming a word line extending in the second horizontal direction along at least one side surface of the vertical channel.

    摘要翻译： 制造垂直沟道晶体管的方法包括：在衬底上形成线状有源图案，以沿第一水平方向延伸; 形成在与所述第一水平方向相交并在所述基板上垂直延伸的第二水平方向隔离所述有源图案的垂直通道; 形成在所述基板上沿所述第一水平方向延伸的掩埋位线; 以及沿所述垂直通道的至少一个侧表面在所述第二水平方向上形成字线。

    METHOD OF FABRICATING VERTICAL CHANNEL TRANSISTOR
    5.
    发明申请
    METHOD OF FABRICATING VERTICAL CHANNEL TRANSISTOR 有权
    制造垂直通道晶体管的方法

    公开(公告)号：US20110143508A1

    公开(公告)日：2011-06-16

    申请号：US12953785

    申请日：2010-11-24

    申请人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    发明人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10885 ,  H01L29/66666 ,  H01L29/7827

    摘要： A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate;forming a buried bit line extending in the first horizontal direction on the substrate; and forming a word line extending in the second horizontal direction along at least one side surface of the vertical channel.

    摘要翻译： 制造垂直沟道晶体管的方法包括：在衬底上形成线状有源图案，以沿第一水平方向延伸; 形成在与所述第一水平方向相交并在所述基板上垂直延伸的第二水平方向隔离所述有源图案的垂直通道; 形成在所述基板上沿所述第一水平方向延伸的掩埋位线; 以及沿所述垂直通道的至少一个侧表面在所述第二水平方向上形成字线。

    Vertical channel transistors and methods for fabricating vertical channel transistors
    6.
    发明授权
    Vertical channel transistors and methods for fabricating vertical channel transistors 有权
    垂直沟道晶体管和制造垂直沟道晶体管的方法

    公开(公告)号：US08372715B2

    公开(公告)日：2013-02-12

    申请号：US13035145

    申请日：2011-02-25

    申请人： Hyun-Woo Chung ,  Hui-Jung Kim ,  Yongchul Oh ,  Hyun-Gi Kim ,  Kang-Uk Kim

    发明人： Hyun-Woo Chung ,  Hui-Jung Kim ,  Yongchul Oh ,  Hyun-Gi Kim ,  Kang-Uk Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66666

    摘要： Provided are a vertical channel transistor and a method for fabricating a vertical channel transistor. The method includes forming an active layer on a substrate, forming a plurality of vertical channels on the active layer, forming a plurality of isolated gate electrodes to surround sidewalls of the plurality of vertical channels, forming a buried bitline to extend along the active layer between the plurality of vertical channels, forming a plug-in between the plurality of vertical channels to connect the plurality of isolated gate electrodes and forming a wordline on a location where the plug-in and the plurality of isolated gate electrodes are connected.

    摘要翻译： 提供一种垂直沟道晶体管和一种用于制造垂直沟道晶体管的方法。 该方法包括在衬底上形成有源层，在有源层上形成多个垂直沟道，形成多个隔离栅电极以围绕多个垂直沟道的侧壁，形成埋置位线，沿着有源层在 所述多个垂直通道在所述多个垂直通道之间形成插入件，以连接所述多个隔离栅电极并在所述插入件和所述多个隔离栅电极连接的位置上形成字线。

    Vertical Channel Transistors And Methods For Fabricating Vertical Channel Transistors
    8.
    发明申请
    Vertical Channel Transistors And Methods For Fabricating Vertical Channel Transistors 有权
    垂直沟道晶体管和制造垂直沟道晶体管的方法

    公开(公告)号：US20110223731A1

    公开(公告)日：2011-09-15

    申请号：US13035145

    申请日：2011-02-25

    申请人： Hyun-Woo Chung ,  Hui-Jung Kim ,  Yongchul Oh ,  Hyun-Gi Kim ,  Kang-Uk Kim

    发明人： Hyun-Woo Chung ,  Hui-Jung Kim ,  Yongchul Oh ,  Hyun-Gi Kim ,  Kang-Uk Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66666

    摘要： Provided are a vertical channel transistor and a method for fabricating a vertical channel transistor. The method includes forming an active layer on a substrate, forming a plurality of vertical channels on the active layer, forming a plurality of isolated gate electrodes to surround sidewalls of the plurality of vertical channels, forming a buried bitline to extend along the active layer between the plurality of vertical channels, forming a plug-in between the plurality of vertical channels to connect the plurality of isolated gate electrodes and forming a wordline on a location where the plug-in and the plurality of isolated gate electrodes are connected.

    摘要翻译： 提供一种垂直沟道晶体管和一种用于制造垂直沟道晶体管的方法。 该方法包括在衬底上形成有源层，在有源层上形成多个垂直沟道，形成多个隔离栅电极以围绕多个垂直沟道的侧壁，形成埋置位线，沿着有源层在 所述多个垂直通道在所述多个垂直通道之间形成插入件，以连接所述多个隔离栅电极并在所述插入件和所述多个隔离栅电极连接的位置上形成字线。

    INTEGRATED CIRCUIT DEVICES INCLUDING LOW-RESISTIVITY CONDUCTIVE PATTERNS IN RECESSED REGIONS
    9.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING LOW-RESISTIVITY CONDUCTIVE PATTERNS IN RECESSED REGIONS 有权
    集成电路设备，包括封闭区域的低电阻率导电模式

    公开(公告)号：US20110017971A1

    公开(公告)日：2011-01-27

    申请号：US12826896

    申请日：2010-06-30

    申请人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    发明人： Kang-Uk Kim ,  Yongchul Oh ,  Hui-Jung Kim ,  Hyun-Woo Chung ,  Hyun-Gi Kim

    IPC分类号： H01L29/78 ,  H01L27/108 ,  H01L27/24

    CPC分类号： H01L27/228 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/2454 ,  H01L27/2463

    摘要： An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar.

    摘要翻译： 集成电路器件包括在半导体衬底上的器件隔离图案，以在其中限定有效区域。 有源区域包括其中的掺杂区域。 导电图案在有源区上延伸并与掺杂区电接触。 导电图案具有比掺杂区域更低的电阻率。 导电图案可以设置在具有低于有源区域的顶表面的底表面的凹陷区域中。 通道柱与掺杂区电接触并从远离衬底的方向从其延伸。 导电栅电极设置在通道柱的侧壁上，并且栅极电介质层设置在沟道柱的栅电极和侧壁之间。

    Vertical pillar transistor
    10.
    发明申请
    Vertical pillar transistor 有权
    立柱晶体管

    公开(公告)号：US20090242975A1

    公开(公告)日：2009-10-01

    申请号：US12382898

    申请日：2009-03-26

    申请人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

    发明人： Hui-Jung Kim ,  Yong-Chul Oh ,  Jae-Man Yoon ,  Hyun-Woo Chung ,  Hyun-Gi Kim ,  Kang-Uk Kim

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/10882 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

    摘要： A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars. The word line may be formed on the second insulation part and may extend between facing sidewalls of the adjacent pair of upper pillars along the first direction.

    摘要翻译： 垂直柱状晶体管可以包括多个下部支柱，多个上部支柱，第一绝缘部分，第二绝缘部分和字线。 多个下支柱基本上垂直于基板突出并且由多个沟槽限定。 多个下柱沿着第二方向延伸并且可以沿着基本上垂直于第二方向的第一方向彼此分离。 多个上柱可以形成在多个下支柱上。 多个上支柱具有比多个下支柱的宽度更小的宽度。 第一绝缘部件在多个下支柱中的每一个的侧壁上具有基本均匀的厚度。 第二绝缘部件可以形成在第一绝缘部分上以填充相邻的上部支柱之间的间隙。 字线可以形成在第二绝缘部分上，并且可以沿着第一方向在相邻的一对上柱的相对侧壁之间延伸。