公开(公告)号：US20130171747A1

公开(公告)日：2013-07-04

申请号：US13769824

申请日：2013-02-19

Applicant: Industrial Technology Research Institute

Inventor： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

IPC: H01L21/66

CPC classification number: H01L22/12 ,  G01N19/04 ,  H01L2224/16

Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

Abstract translation: 提供了半导体器件和机械完整性测试装置的制造方法和测试方法。 一种物体包括晶片，绝缘层和多个导电柱。 晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。 绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。 执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。 在机械完整性测试中，在第一盲孔中的导电柱被限定之后，芯片区域中的导电柱电连接到元件。

公开(公告)号：US09252054B2

公开(公告)日：2016-02-02

申请号：US14484970

申请日：2014-09-12

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Sheng-Tsai Wu ,  Heng-Chieh Chien ,  John H. Lau ,  Yu-Lin Chao ,  Wei-Chung Lo

IPC: H01L23/367 ,  H01L21/768 ,  H01L21/48 ,  H01L23/42 ,  H01L23/427 ,  H01L23/433 ,  H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L21/76898 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/433 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16235 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.

Abstract translation: 公开了一种薄型集成电路器件及其制造方法。 制造工艺包括在衬底上形成贯通硅通孔（TSV），将TSV的第一端子暴露在衬底的第一表面上，在衬底的第一表面上设置凸块以使凸块电连接到 所述TSV在所述突起上设置集成电路芯片（IC），使得所述IC的第一侧连接到所述凸块，在所述IC的第二侧的第二侧上设置热界面材料（TIM）层， IC，通过TIM层将散热器帽附接到IC上，并且背衬研磨衬底的第二表面以在承载散热器盖的同时将TSV暴露于衬底的第二表面。

公开(公告)号：US08673658B2

公开(公告)日：2014-03-18

申请号：US13769824

申请日：2013-02-19

Applicant: Industrial Technology Research Institute

Inventor： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

IPC: H01L21/12

CPC classification number: H01L22/12 ,  G01N19/04 ,  H01L2224/16

Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

Abstract translation: 提供了半导体器件和机械完整性测试装置的制造方法和测试方法。 一种物体包括晶片，绝缘层和多个导电柱。 晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。 绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。 执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。 在机械完整性测试中，在第一盲孔中的导电柱合格之后，芯片区域中的导电柱电连接到元件。