-
公开(公告)号：US09412626B2
公开(公告)日：2016-08-09
申请号：US14935510
申请日：2015-11-09
Applicant: Infineon Technologies AG
Inventor： Ralf Otremba , Josef Hoeglauer , Juergen Schredl , Xaver Schloegel , Klaus Schiess , Bernd Roemer , Edward Fuergut
IPC: H01L21/00 , H01L21/56 , H01L23/34 , H01L23/495 , H01L23/31 , H01L23/00 , H01L23/552
CPC classification number: H01L21/565 , H01L21/56 , H01L23/3107 , H01L23/3135 , H01L23/34 , H01L23/495 , H01L23/49562 , H01L23/49568 , H01L23/552 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/16245 , H01L2224/32245 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/8592 , H01L2224/97 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/29099
Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.
Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。
-
公开(公告)号：US20160064255A1
公开(公告)日：2016-03-03
申请号：US14935510
申请日：2015-11-09
Applicant: Infineon Technologies AG
Inventor： Ralf Otremba , Josef Hoeglauer , Juergen Schredl , Xaver Schloegel , Klaus Schiess , Bernd Roemer , Edward Fuergut
IPC: H01L21/56
CPC classification number: H01L21/565 , H01L21/56 , H01L23/3107 , H01L23/3135 , H01L23/34 , H01L23/495 , H01L23/49562 , H01L23/49568 , H01L23/552 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/16245 , H01L2224/32245 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/8592 , H01L2224/97 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/29099
Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.
Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。
-
公开(公告)号：US09184066B2
公开(公告)日：2015-11-10
申请号：US13678577
申请日：2012-11-16
Applicant: Infineon Technologies AG
Inventor： Ralf Otremba , Josef Hoeglauer , Juergen Schredl , Xaver Schloegel , Klaus Schiess , Bernd Roemer , Edward Fuergut
IPC: H01L23/552 , H01L21/56 , H01L23/31 , H01L23/495 , H01L23/00
CPC classification number: H01L21/565 , H01L21/56 , H01L23/3107 , H01L23/3135 , H01L23/34 , H01L23/495 , H01L23/49562 , H01L23/49568 , H01L23/552 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/16245 , H01L2224/32245 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/8592 , H01L2224/97 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/29099
Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.
Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。
-
公开(公告)号：US20140138803A1
公开(公告)日：2014-05-22
申请号：US13678577
申请日：2012-11-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Ralf Otremba , Josef Hoeglauer , Juergen Schredl , Xaver Schloegel , Klaus Schiess , Bernd Roemer , Edward Fuergut
IPC: H01L23/34 , H01L23/552 , H01L21/56 , H01L23/495
CPC classification number: H01L21/565 , H01L21/56 , H01L23/3107 , H01L23/3135 , H01L23/34 , H01L23/495 , H01L23/49562 , H01L23/49568 , H01L23/552 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/06181 , H01L2224/16245 , H01L2224/32245 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/48824 , H01L2224/48847 , H01L2224/73265 , H01L2224/8592 , H01L2224/97 , H01L2924/00014 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/29099
Abstract: A chip arrangement is provided, the chip arrangement including: a carrier; a chip disposed over the carrier, the chip including one or more contact pads, wherein a first contact pad of the one or more contact pads is electrically contacted to the carrier; a first encapsulation material at least partially surrounding the chip; and a second encapsulation material at least partially surrounding the first encapsulation material.
Abstract translation: 提供了芯片布置，芯片布置包括：载体; 芯片，其设置在所述载体上方，所述芯片包括一个或多个接触焊盘，其中所述一个或多个接触焊盘的第一接触焊盘与所述载体电接触; 至少部分地围绕所述芯片的第一封装材料; 以及至少部分地围绕所述第一包封材料的第二包封材料。
-
-
-
Search Results
4
records
(took 0.036 seconds)
