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    Oscillator Devices and Methods
    4.
    发明申请
    Oscillator Devices and Methods 有权
    振荡器装置和方法

    公开(公告)号：US20150180483A1

    公开(公告)日：2015-06-25

    申请号：US14138290

    申请日：2013-12-23

    申请人： INFINEON TECHNOLOGIES AG

    发明人： David Astrom ,  Andreas Fugger ,  Herwig Wappis

    IPC分类号： H03L7/06

    CPC分类号： H03L7/06 ,  H03K3/0231 ,  H03L7/00 ,  H03L7/02 ,  H03L7/18

    摘要： Oscillator devices and corresponding methods are disclosed. In some embodiments an apparatus includes an oscillator circuit arrangement, a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement and a reference resistor circuit. The apparatus further includes a sample and hold circuit, wherein a first input of the sample and hold circuit is coupled to an output of the reference resistor circuit and a second input of the sample and hold circuit is coupled to an output of the frequency variable resistor circuit, wherein an output of the sample and hold circuit is coupled with an input of the oscillator circuit arrangement.

    摘要翻译： 公开了振荡器装置和相应的方法。 在一些实施例中，一种装置包括振荡器电路装置，耦合到振荡器电路装置的输出的频率可变电阻电路和参考电阻电路。 该装置还包括采样和保持电路，其中采样和保持电路的第一输入耦合到参考电阻电路的输出，并且采样和保持电路的第二输入耦合到频率可变电阻器 电路，其中所述采样和保持电路的输出与所述振荡器电路装置的输入耦合。

    Oscillator devices and methods
    5.
    发明授权
    Oscillator devices and methods 有权
    振荡器装置和方法

    公开(公告)号：US09444468B2

    公开(公告)日：2016-09-13

    申请号：US14138290

    申请日：2013-12-23

    申请人： Infineon Technologies AG

    发明人： David Astrom ,  Andreas Fugger ,  Herwig Wappis

    IPC分类号： H03K3/26 ,  H03L7/06 ,  H03L7/18 ,  H03L7/02 ,  H03L7/00 ,  H03K3/0231

    CPC分类号： H03L7/06 ,  H03K3/0231 ,  H03L7/00 ,  H03L7/02 ,  H03L7/18

    摘要： Oscillator devices and corresponding methods are disclosed. In some embodiments an apparatus includes an oscillator circuit arrangement, a frequency variable resistor circuit coupled to an output of the oscillator circuit arrangement and a reference resistor circuit. The apparatus further includes a sample and hold circuit, wherein a first input of the sample and hold circuit is coupled to an output of the reference resistor circuit and a second input of the sample and hold circuit is coupled to an output of the frequency variable resistor circuit, wherein an output of the sample and hold circuit is coupled with an input of the oscillator circuit arrangement.

    摘要翻译： 公开了振荡器装置和相应的方法。 在一些实施例中，一种装置包括振荡器电路装置，耦合到振荡器电路装置的输出的频率可变电阻电路和参考电阻电路。 该装置还包括采样和保持电路，其中采样和保持电路的第一输入耦合到参考电阻电路的输出，并且采样和保持电路的第二输入耦合到频率可变电阻器 电路，其中所述采样和保持电路的输出与所述振荡器电路装置的输入耦合。

    SYSTEMS AND METHODS FOR HIGH VOLTAGE BRIDGE BIAS GENERATION AND LOW VOLTAGE READOUT CIRCUITRY
    6.
    发明申请
    SYSTEMS AND METHODS FOR HIGH VOLTAGE BRIDGE BIAS GENERATION AND LOW VOLTAGE READOUT CIRCUITRY 有权
    用于高电压桥梁偏差生成和低电压读出电路的系统和方法

    公开(公告)号：US20150316586A1

    公开(公告)日：2015-11-05

    申请号：US14265456

    申请日：2014-04-30

    申请人： Infineon Technologies AG

    发明人： Dirk Hammerschmidt ,  Peter Bogner ,  David Astrom

    IPC分类号： G01R17/06 ,  G01R19/00

    CPC分类号： G01R17/06 ,  G01D3/036 ,  G01L9/12 ,  G01R19/0084 ,  H02M3/07

    摘要： A multi voltage sensor system includes one or more charge pumps, a sensor bridge and readout circuitry. The one or more charge pumps are configured to provide a high voltage. The sensor bridge is biased by the high voltage and is configured to provide sensor values. The readout circuitry includes only low voltage components. The readout circuitry is configured to receive the sensor values.

    摘要翻译： 多电压传感器系统包括一个或多个电荷泵，传感器桥和读出电路。 一个或多个电荷泵被配置成提供高电压。 传感器桥被高电压偏置，并配置为提供传感器值。 读出电路仅包括低电压分量。 读出电路被配置为接收传感器值。

    Driver Circuit for a Digital Signal Transmitting Bus
    7.
    发明申请
    Driver Circuit for a Digital Signal Transmitting Bus 有权
    数字信号传输总线的驱动电路

    公开(公告)号：US20140091833A1

    公开(公告)日：2014-04-03

    申请号：US13631925

    申请日：2012-09-29

    申请人： INFINEON TECHNOLOGIES AG

    发明人： David Astrom ,  Daniel Mandler

    IPC分类号： H03K19/003

    CPC分类号： H04L25/0272 ,  H04L12/40006 ,  H04L12/40032 ,  H04L25/0264 ,  H04L2012/40215 ,  H04L2012/40234 ,  H04L2012/40241 ,  H04L2012/40273

    摘要： A driver circuit for a digital signal transmitting bus includes a main switch. The main switch is connected to the bus, is controllable by the digital signal to be transmitted, and has one on-switching state in which it has maximum electrical conductivity, one off-switching state in which it has minimum electrical conductivity and at least one intermediate switching state with an electrical conductivity between the minimum and maximum conductivity. The digital signal has a first logic state and a second logic state, the first logic state controls the main switch to be in the on-switching state and the second logic state controls the main switch to be in the off-switching state. The main switch is in the intermediate switching state during switching from the on-switching state to the off-switching state and/or vice versa.

    摘要翻译： 数字信号发送总线的驱动电路包括主开关。 主开关连接到总线，由要传输的数字信号控制，并具有一个导通状态，其中它具有最大的导电性，一个断开状态，其中具有最小导电性和至少一个 具有最小和最大导电率之间的导电性的中间开关状态。 数字信号具有第一逻辑状态和第二逻辑状态，第一逻辑状态控制主开关处于导通状态，第二逻辑状态控制主开关处于断开状态。 在从开关状态切换到断开状态和/或反之亦然时，主开关处于中间开关状态。

    Bus driver circuit with improved transition speed
    10.
    发明授权
    Bus driver circuit with improved transition speed 有权
    总线驱动电路具有提高的转换速度

    公开(公告)号：US09495317B2

    公开(公告)日：2016-11-15

    申请号：US14132831

    申请日：2013-12-18

    申请人： Infineon Technologies AG

    发明人： Dieter Metzner ,  Peter Widerin ,  David Astrom

    IPC分类号： G06F13/00 ,  G06F13/40

    CPC分类号： G06F13/4022 ,  G06F2211/002

    摘要： A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

    摘要翻译： 总线驱动器电路可以包括第一和第二电路节点，其中第一电路节点可操作地耦合到总线线路，这导致第一和第二电路节点之间的总线电容。 开关电路耦合到第一电路节点并被配置为在第一和第二电路节点之间施加输出电压。 从而当控制信号表示主导状态时，总线电容被充电。 放电电路包括至少一个电阻器。 放电电路耦合在第一和第二电路节点之间，并且被配置为当控制信号指示隐性状态时允许总线电容经由电阻放电。 开关电路还被配置为提供用于在从显性状态到隐性状态的过渡期期间对总线电容放电的临时电流通路。