公开(公告)号：US09305874B2

公开(公告)日：2016-04-05

申请号：US14251609

申请日：2014-04-13

Applicant: Infineon Technologies AG

Inventor： Fabio Brucchi ,  Davide Chiola

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L21/4875 ,  H01L21/4878 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/32 ,  H01L25/072 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0715 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/014

Abstract: Various embodiments provide a baseplate for an electronic module, wherein the baseplate comprises a conductive material; and a recess formed in one main surface of the baseplate and being adapted to accommodate an electronic chip.

公开(公告)号：US10109544B2

公开(公告)日：2018-10-23

申请号：US15630750

申请日：2017-06-22

Applicant: Infineon Technologies AG

Inventor： Fabio Brucchi ,  Davide Chiola

IPC: H01L23/043 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L25/07 ,  H01L25/11 ,  H01L21/48 ,  H01L23/492 ,  H01L23/367 ,  H01L23/373 ,  H01L21/56

Abstract: Various embodiments provide an electronic module comprising a baseplate. A recess is formed in one main surface of the baseplate, wherein the recess is adapted to accommodate an electronic chip. The electronic chip is attached to a substrate or carrier and is placed in the recess.

公开(公告)号：US09716018B2

公开(公告)日：2017-07-25

申请号：US15070942

申请日：2016-03-15

Applicant: Infineon Technologies AG

Inventor： Fabio Brucchi ,  Davide Chiola

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/13 ,  H01L23/36 ,  H01L23/373 ,  H01L25/11 ,  H01L21/56

CPC classification number: H01L23/13 ,  H01L21/4875 ,  H01L21/4878 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/32 ,  H01L25/072 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0715 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/014

Abstract: Various embodiments provide methods for manufacturing a baseplate for an electronic module and an electronic module comprising a baseplate, wherein the baseplate comprises a conductive material; and a recess formed in one main surface of the baseplate and being adapted to accommodate an electronic chip.

公开(公告)号：US09082759B2

公开(公告)日：2015-07-14

申请号：US13686767

申请日：2012-11-27

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Fabio Brucchi

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

Abstract translation: 根据本发明的一个实施例，一种半导体封装包括一个管芯焊盘和一个设置在管芯焊盘周围的密封剂。 半导体封装具有第一侧壁和第二侧壁。 第二侧壁垂直于第一侧壁。 第一侧壁和第二侧壁限定拐角区域。 连接杆设置在密封剂内。 连接杆连接模片，并延伸离开模具桨。 在拐角区域设置虚拟引线。 虚拟引线不与半导体封装内的另一导电部件电耦合。 虚拟引线和连接杆之间的距离小于连接条与半导体封装中的其它引线或其他连接条之间的最短距离。

公开(公告)号：US20140145318A1

公开(公告)日：2014-05-29

申请号：US13686767

申请日：2012-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Fabio Brucchi

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

Abstract translation: 根据本发明的一个实施例，一种半导体封装包括一个管芯焊盘和一个设置在管芯焊盘周围的密封剂。 半导体封装具有第一侧壁和第二侧壁。 第二侧壁垂直于第一侧壁。 第一侧壁和第二侧壁限定拐角区域。 连接杆设置在密封剂内。 连接杆连接模片，并延伸离开模具桨。 在拐角区域设置虚拟引线。 虚拟引线不与半导体封装内的另一导电部件电耦合。 虚拟引线和连接杆之间的距离小于连接条与半导体封装中的其它引线或其他连接条之间的最短距离。