公开(公告)号：US20250149501A1

公开(公告)日：2025-05-08

申请号：US19013849

申请日：2025-01-08

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20220367104A1

公开(公告)日：2022-11-17

申请号：US17873518

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01F27/28 ,  H01F27/02 ,  H01F27/24

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US20210398941A1

公开(公告)日：2021-12-23

申请号：US17466842

申请日：2021-09-03

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20240063173A1

公开(公告)日：2024-02-22

申请号：US18385167

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L25/50 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2224/16235 ,  H01L2224/16113

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20220359115A1

公开(公告)日：2022-11-10

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304933A1

公开(公告)日：2019-10-03

申请号：US15938114

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20170154828A1

公开(公告)日：2017-06-01

申请号：US14953779

申请日：2015-11-30

Applicant: INTEL CORPORATION

Inventor： Timothy A. GOSSELIN ,  Patrick NARDI ,  Kartik SRINIVASAN ,  Amram EITAN ,  Ji Yong PARK ,  Christopher L. RUMER ,  George S. KOSTIEW

IPC: H01L21/66 ,  B23K20/02 ,  B23K20/00 ,  H01L23/00

CPC classification number: H01L22/12 ,  B23K1/0016 ,  B23K20/002 ,  B23K20/026 ,  B23K20/16 ,  B23K20/233 ,  B23K20/24 ,  B23K20/26 ,  B23K31/12 ,  B23K2101/42 ,  H01L22/20 ,  H01L24/14 ,  H01L24/75 ,  H01L2224/81192 ,  H01L2924/351

Abstract: A method and machine-readable medium including non-transitory program instructions that when executed by a processor cause the processor to perform a method including measuring at least one parameter of a substrate or a die; and establishing or modifying a thermal compression bonding recipe based on the at least one parameter, wherein the thermal compression bonding recipe is operable for thermal compression bonding of the die and the substrate. A thermal compression bonding tool including a pedestal operable to hold a substrate during a thermal compression bonding process and a bond head operable to engage a die, the tool including a controller machine readable instructions to process a substrate and a die combination, the instructions including an algorithm to implement or modify a thermal compression bonding process based on a parameter of a substrate or die.

公开(公告)号：US20200266149A1

公开(公告)日：2020-08-20

申请号：US16646932

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng XU ,  Junnan ZHAO ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

公开(公告)号：US20200027856A1

公开(公告)日：2020-01-23

申请号：US16586820

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

公开(公告)号：US20200006180A1

公开(公告)日：2020-01-02

申请号：US16024697

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Andrew BROWN ,  Ji Yong PARK ,  Siddharth ALUR ,  Cheng XU ,  Amruthavalli ALUR

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/29

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.