公开(公告)号：US09984038B2

公开(公告)日：2018-05-29

申请号：US15007450

申请日：2016-01-27

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan

IPC: G06F1/00 ,  G06F1/32 ,  G06F15/82 ,  G06F1/20 ,  G06F9/06 ,  G06F15/76 ,  G06F1/08 ,  G06F9/30

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

公开(公告)号：US08806248B2

公开(公告)日：2014-08-12

申请号：US14041688

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan ,  Ofer Nathan ,  Tomer Ziv

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

公开(公告)号：US09280172B2

公开(公告)日：2016-03-08

申请号：US14140875

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan

IPC: G06F1/08 ,  G06F1/20 ,  G06F1/32 ,  G06F9/06 ,  G06F15/76

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

公开(公告)号：US08769323B2

公开(公告)日：2014-07-01

申请号：US13788547

申请日：2013-03-07

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev Jahagirdar ,  Oren Lamdan ,  Ofer Nathan ,  Tomer Ziv

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

Abstract translation: 随着对多核处理器的进展，每个核心都不能容易地确定另一个模具相对于空闲或活动状态的状态。 讨论了在多芯片微处理器中利用接口在多个核心之间传输核心状态的提议。 因此，这通过允许基于利用每个核心状态来设置性能和频率的最佳设置来促进热管理。

公开(公告)号：US09904346B2

公开(公告)日：2018-02-27

申请号：US14716326

申请日：2015-05-19

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Ohad Falik ,  Jose P. Allarey

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5027 ,  G06F9/5094 ,  G06F2209/501 ,  Y02D10/126 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D50/20

Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

公开(公告)号：US20160140081A1

公开(公告)日：2016-05-19

申请号：US15007450

申请日：2016-01-27

Applicant: Intel Corporation

Inventor： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan

IPC: G06F15/82 ,  G06F9/30

CPC classification number: G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

Abstract: With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

公开(公告)号：US20150253833A1

公开(公告)日：2015-09-10

申请号：US14716326

申请日：2015-05-19

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Ohad Falik ,  Jose P. Allarey

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5027 ,  G06F9/5094 ,  G06F2209/501 ,  Y02D10/126 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/26 ,  Y02D50/20

Abstract: Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses.

Abstract translation: 介绍了一种改善事件处理性能的装置的实施例。 在一个实施例中，该装置包括多个处理元件和任务布线逻辑。 如果至少一个处理元件处于turbo模式，则任务路由逻辑至少基于性能损失的比较来选择用于执行任务的处理元件。

公开(公告)号：US08732399B2

公开(公告)日：2014-05-20

申请号：US13787311

申请日：2013-03-06

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  Jose P. Allarey

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1048 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.

Abstract translation: 根据至少一个实施例的在低功率模式下保持缓存信息的技术。 在一个实施例中，存储在处理器的本地高速缓存中的信息在处理器被置于低功率模式之前被保存到共享高速缓存，使得其他处理器可以从共享高速缓存访​​问信息，而不是使低功率模式处理器从 低功耗模式来访问其本地缓存。