公开(公告)号：US20240145395A1

公开(公告)日：2024-05-02

申请号：US18406018

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20160172222A1

公开(公告)日：2016-06-16

申请号：US15050387

申请日：2016-02-22

Applicant: INTEL CORPORATION

Inventor： John C. JOHNSON ,  Sandeep B. SANE ,  Sandeep RAZDAN ,  Edward R. PRACK ,  Leonel R. ARANA ,  Peter A. DAVISON ,  Eric J. MORET ,  Lawrence M. PALANUK ,  Gregory A. STONE

IPC: H01L21/673 ,  H01L21/683 ,  H01L21/78 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

公开(公告)号：US20220100692A1

公开(公告)日：2022-03-31

申请号：US17033593

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Dheeraj SUBBAREDDY ,  Ankireddy NALAMALPU ,  Anshuman THAKUR ,  MD Altaf HOSSAIN ,  Mahesh KUMASHIKAR ,  Kemal AYGÜN ,  Casey THIELEN ,  Daniel KLOWDEN ,  Sandeep B. SANE

IPC: G06F13/42

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

公开(公告)号：US20200211969A1

公开(公告)日：2020-07-02

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20230085944A1

公开(公告)日：2023-03-23

申请号：US17482843

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Bai NIE ,  Brandon C. MARIN ,  Sandeep B. SANE ,  Leonel ARANA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises an organic material. In an embodiment, a via is provided through a thickness of the core. In an embodiment, a shell is around the via, where the shell comprises a magnetic material. In an embodiment, a mold layer is over the core, and a bridge is embedded in the mold layer. In an embodiment, a column is through the mold layer, where the column is aligned with the via.

公开(公告)号：US20170032991A1

公开(公告)日：2017-02-02

申请号：US15295943

申请日：2016-10-17

Applicant: INTEL CORPORATION

Inventor： John C. JOHNSON ,  Sandeep B. SANE ,  Sandeep RAZDAN ,  Edward R. PRACK ,  Leonel R. ARANA ,  Peter A. DAVISON ,  Eric J. MORET ,  Lawrence M. PALANUK ,  Gregory A. STONE

IPC: H01L21/673 ,  H01L21/78 ,  H01L21/683 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/67333 ,  H01L21/67265 ,  H01L21/67309 ,  H01L21/67356 ,  H01L21/67363 ,  H01L21/67383 ,  H01L21/67769 ,  H01L21/67772 ,  H01L21/67778 ,  H01L21/68 ,  H01L21/6833 ,  H01L21/68764 ,  H01L21/68771 ,  H01L21/78 ,  H05K13/0084

Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.

Abstract translation: 一种方法包括识别晶片上的多个管芯的晶片位置，将多个管芯中的每个管芯的晶片位置存储在数据库中，将晶片切割成多个单个管芯，将每个单模管芯定位在管芯中 在托盘上的位置位置，并将模具位置存储在数据库中的每个单个模具的托盘上。 数据库包括包括与每个模具位置相关联的晶片位置的信息。 托盘被运送到处理工具，并且多个分割模具中的至少一个从托盘上的模具位置移除并在处理工具中进行处理。 在处理之前，单独模具位于托盘上的相同的限定位置处理被处理的单个模具。 描述和要求保护其他实施例。