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    TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE
    2.
    发明公开
    TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE 审中-公开

    公开(公告)号：US20230400908A1

    公开(公告)日：2023-12-14

    申请号：US18196309

    申请日：2023-05-11

    Applicant: Intel Corporation

    Inventor： BINATA BHATTACHARYYA ,  PAUL S. DIEFENBAUGH

    IPC: G06F1/3287 ,  G06F1/3206 ,  G06F3/06 ,  G06F9/30 ,  G06F12/06

    CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F3/0625 ,  G06F9/30098 ,  G06F12/0607 ,  G06F3/064 ,  G06F3/0679

    Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

    TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE
    3.
    发明申请
    TECHNIQUES FOR MEMORY ACCESS IN A REDUCED POWER STATE 有权

    公开(公告)号：US20220066535A1

    公开(公告)日：2022-03-03

    申请号：US17522294

    申请日：2021-11-09

    Applicant: Intel Corporation

    Inventor： BINATA BHATTACHARYYA ,  PAUL S. DIEFENBAUGH

    IPC: G06F1/3287 ,  G06F1/3206 ,  G06F3/06 ,  G06F9/30 ,  G06F12/06

    Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

    TECHNIQUES FOR MANAGING SYSTEM POWER USING DEFERRED GRAPHICS RENDERING
    5.
    发明申请
    TECHNIQUES FOR MANAGING SYSTEM POWER USING DEFERRED GRAPHICS RENDERING 有权
    使用延迟图形渲染来管理系统电源的技术

    公开(公告)号：US20160370848A1

    公开(公告)日：2016-12-22

    申请号：US15050222

    申请日：2016-02-22

    Applicant: INTEL CORPORATION

    Inventor： NITHYANANDA S. JEGANATHAN ,  RAJESH POORNACHANDRAN ,  PAUL S. DIEFENBAUGH ,  KYUNGTAE HAN

    IPC: G06F1/32 ,  G06T1/20

    CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06T1/20

    Abstract: An apparatus may include a memory to store one or more graphics rendering commands in a queue after generation. The apparatus may also include a processor circuit, and a graphics rendering command manager for execution on the processor to dynamically determine at one or more instances a total execution duration for the one or more graphics rendering commands, where the total execution duration comprises a total time to render the one or more graphics rendering commands. The graphics rendering command manager also may be for execution on the processor to generate a signal to transmit the one or more graphics rendering commands for rendering by a graphics processor when the total execution duration exceeds a graphics rendering command execution window.

    Abstract translation: 一种装置可以包括存储器，用于在生成之后在队列中存储一个或多个图形呈现命令。 该装置还可以包括处理器电路和用于在处理器上执行的图形渲染命令管理器，以在一个或多个实例上动态地确定一个或多个图形渲染命令的总执行持续时间，其中总执行持续时间包括总时间 渲染一个或多个图形渲染命令。 图形渲染命令管理器还可以在处理器上执行以产生一个信号，以在总执行持续时间超过图形渲染命令执行窗口时传送一个或多个图形渲染命令，以供图形处理器渲染。

    METHOD AND APPARATUS FOR DETERMINING THREAD EXECUTION PARALLELISM
    6.
    发明申请
    METHOD AND APPARATUS FOR DETERMINING THREAD EXECUTION PARALLELISM 有权
    用于确定螺纹执行并联的方法和装置

    公开(公告)号：US20150379668A1

    公开(公告)日：2015-12-31

    申请号：US14319099

    申请日：2014-06-30

    Applicant: Intel Corporation

    Inventor： ELIEZER WEISSMANN ,  ARIK GIHON ,  EFRAIM ROTEM ,  PAUL S. DIEFENBAUGH ,  ERIC C. SAMSON ,  MICHAEL MISHAELI ,  YONI AIZIK ,  CHEN RANEL

    IPC: G06T1/20 ,  G09G5/18

    CPC classification number: G06F9/5044 ,  G06F3/14 ,  G06F9/5083 ,  G09G2360/08

    Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.

    Abstract translation: 一种用于确定线程执行并行性的装置和方法。 例如，根据一个实施例的处理器包括：多个核，用于执行多个线程; 多个计数器，用于收集与所述多个核上的所述多个线程的执行相关的数据; 依赖关系分析模块，用于分析与线程的执行有关的数据，并且响应地确定线程间相关性的级别; 以及控制模块，用于基于确定的线程间依赖性水平来响应地调整多个核心的操作。

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