公开(公告)号：US20160191420A1

公开(公告)日：2016-06-30

申请号：US14583613

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Michael Todd Frederick

IPC: H04L12/947 ,  H04L12/743

CPC classification number: H04L49/25 ,  H04L45/7453 ,  H04L49/109 ,  H04L49/356

Abstract: In an example, selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system is divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. The two pipelines do not reconverge until after memory values have been returned. However, the uncore fabric may still present a single, monolithic interface to requesting devices. This allows system designers to treat the uncore fabric as a “black box” without modifying existing designs. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

Abstract translation: 在一个示例中，片上系统（SoC）或其他嵌入式系统的非空心结构的选定部分被分成两个独立的管道。 每个流水线独立于其他流水线运行，并且每个流水线仅访问系统存储器的一半，例如交错存储器中的偶数或奇数地址。 在返回内存值之后，两条管道不会重新映射。 然而，不织布可能仍然呈现单个的单片接口来请求设备。 这允许系统设计人员将不织布织物视为“黑匣子”，而无需修改现有设计。 每个传入地址可以通过确定性散列来处理，分配给其中一条管道，通过存储器处理，然后传递给信用回报。

公开(公告)号：US20160188529A1

公开(公告)日：2016-06-30

申请号：US14583142

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Michael T. Klinglesmith ,  Marc Torrant ,  James A. Coleman ,  Peter J. Elardo ,  Eric A. Geisler

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/18 ,  G06F12/08

CPC classification number: G06F15/7814 ,  G06F12/0811 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/18 ,  G06F15/781 ,  G06F2212/314 ,  Y02D10/13 ,  Y02D10/14

Abstract: In an example, a control system may include a system-on-a-chip (SoC), including one processor for real-time operation to manage devices in the control system, and another processor configured to execute auxiliary functions such as a user interface for the control system. The first core and second core may share memory such as dynamic random access memory (DRAM), and may also share an uncore fabric configured to communicatively couple the processors to one or more peripheral devices. The first core may require a guaranteed quality of service (QoS) to memory and/or peripherals. The uncore fabric may be divided into a first “real-time” virtual channel designated for traffic from the first processor, and a second “auxiliary” virtual channel designated for traffic from the second processor. The uncore fabric may apply a suitable selection or weighting algorithm to the virtual channels to guarantee the QoS.

Abstract translation: 在一个示例中，控制系统可以包括片上系统（SoC），其包括用于实时操作的一个处理器来管理控制系统中的设备，以及另一处理器，其被配置为执行辅助功能，例如用户接口 用于控制系统。 第一核心和第二核心可以共享诸如动态随机存取存储器（DRAM）的存储器，并且还可以共享被配置为将处理器通信地耦合到一个或多个外围设备的非空心结构。 第一个核心可能需要对存储器和/或外设的有保证的服务质量（QoS）。 非空心结构可以被划分为从第一处理器指定用于业务的第一“实时”虚拟通道和被指定用于来自第二处理器的业务的第二“辅助”虚拟通道。 不织布可以对虚拟信道应用合适的选择或加权算法来保证QoS。

公开(公告)号：US11372674B2

公开(公告)日：2022-06-28

申请号：US17080970

申请日：2020-10-27

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F13/42 ,  G06F15/78 ,  G06F15/76

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US20220113967A1

公开(公告)日：2022-04-14

申请号：US17561197

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Reddy Pamu ,  Lakshminarayana Pappu ,  David J. Harriman ,  Debra Bernstein ,  Ramadass Nagarajan

IPC: G06F9/30 ,  G06T1/20 ,  G06T1/60

Abstract: A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a fabric comprising a handler circuitry to decode a request from a compute engine, the handler circuitry to route the request based on an opcode included in the request, the handler configured to decode the opcode from a set of opcodes for use in requests by the compute engine, wherein the set of opcodes include opcodes corresponding to a first write request type and a first read request type, wherein requests of the first write request type and the first read request type are routed to either the host memory or the graphics memory; and a second write request type and a second read request type, wherein requests of the second write request type and the second request type are to be routed to the sideband network.

公开(公告)号：US09971711B2

公开(公告)日：2018-05-15

申请号：US14583156

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Michael T. Klinglesmith ,  Joydeep Ray

IPC: G06F13/16 ,  G06F15/78

CPC classification number: G06F13/1615 ,  G06F13/1663 ,  G06F15/7821 ,  Y02D10/14

Abstract: Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. However, the two pipelines are tightly coupled to maintain coherency of the fabric. Coupling may be accomplished, for example, by a shared clock that is one-half of the base clock cycle for the fabric. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.

公开(公告)号：US20230027585A1

公开(公告)日：2023-01-26

申请号：US17954430

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Lichen Weng ,  Ramadass Nagarajan ,  Anand Jayaraman ,  Vijeta Prasad ,  Justin Reyes ,  Gurucharapathy Karthikeyan

IPC: H04L45/745 ,  H04L49/109 ,  H04L45/16

Abstract: In one embodiment, a first chiplet includes: a plurality of agents to generate messages, each of the messages having a destination port identifier comprising a first portion to identify a destination chiplet and a second portion to identify a destination agent on the destination chiplet; a die-to die bridge to couple the first chiplet to a second chiplet; a fabric coupled to the die-to-die bridge to route communications between the plurality of agents, where a first agent is to generate a first message having a first destination port identifier; and a first fabric adapter coupled to the first agent, the first fabric adapter to direct the first message to the die-to-die bridge when the first portion of the first destination port identifier identifies a second chiplet as the destination chiplet. Other embodiments are described and claimed.

公开(公告)号：US20220114131A1

公开(公告)日：2022-04-14

申请号：US17558945

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  David J. Harriman ,  Ramadass Nagarajan ,  Mahesh S. Natu

IPC: G06F13/42

Abstract: In one embodiment, a device includes: an interface circuit to couple the device to a host via a link, where in a first mode the interface circuit is to be configured as an integrated switch controller and in a second mode the interface circuit is to be configured as a link controller; and a fabric coupled to the interface circuit, the fabric to couple to a plurality of hardware circuits, where the fabric is to be dynamically configured for one of the first mode or the second mode based on link training of the link. Other embodiments are described and claimed.

公开(公告)号：US10133670B2

公开(公告)日：2018-11-20

申请号：US14583611

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Jose S. Niell ,  Michael T. Klinglesmith ,  Derek T. Bachand ,  Ganesh Kumar

IPC: G06F12/0815 ,  G06F13/28 ,  G06F13/42

Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

公开(公告)号：US09563579B2

公开(公告)日：2017-02-07

申请号：US13780117

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Ravishankar Iyer ,  Quang T. Le ,  Ravi Kolagotla ,  Ioannis T. Schoinas ,  Jose S. Niell

IPC: G06F13/00 ,  G06F9/00 ,  G06F13/16

CPC classification number: G06F13/00 ,  G06F9/00 ,  G06F13/1626 ,  Y02D10/14

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。

公开(公告)号：US09075952B2

公开(公告)日：2015-07-07

申请号：US13743833

申请日：2013-01-17

Applicant: Intel Corporation

Inventor： Jose S. Niell ,  Ramadass Nagarajan

IPC: G06F15/78

CPC classification number: G06F15/7807 ,  G06F13/4059 ,  G06F21/70 ,  G06F2213/0026 ,  G06F2213/0038 ,  G06F2221/2101 ,  G06F2221/2141 ,  H04L47/622

Abstract: In one embodiment, a fabric of a processor such as a system on a chip includes at least one data buffer including a plurality of entries each to store data to be transferred to and from a plurality of agents and to and from a memory, a request tracker to maintain track of pending requests to be output to an ordered domain of the fabric, and an output throttle logic to control allocation into the ordered domain between write transactions from a core agent and read completion transactions from the memory. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，诸如芯片上的系统的处理器的结构包括至少一个数据缓冲器，其包括多个条目，每个条目用于存储要传送到多个代理和从存储器传送到和从存储器传输的数据，请求 跟踪器，以跟踪要输出到结构的有序域的待处理请求;以及输出节流逻辑，用于控制从核心代理的写入事务和从存储器读取完成事务之间对有序域的分配。 描述和要求保护其他实施例。