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公开(公告)号：US20160299559A1
公开(公告)日：2016-10-13
申请号：US15134770
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US20160380809A1
公开(公告)日：2016-12-29
申请号：US14752524
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Zhaorong Hou , Bryan Hunt , Michael Beale , David O. Novick , Carlos Carrizo , Rameshkumar G. Illikkal , Srinivas Sundaravaradan , Francisco M. Casares , Mark P. Baldwin , Krishna Surya
CPC classification number: H04W4/80 , H04L12/10 , H04L41/0806 , H04L41/0856 , H04L63/0428 , H04L67/12 , H04L67/34 , H04W4/50 , H04W4/70
Abstract: Systems, methods, and apparatus to configure embedded devices are described. An example apparatus includes a network interface to communicatively couple the apparatus with a network, an antenna to receive a radio frequency signal including 1) configuration data and 2) power, a memory coupled to the antenna to receive the power and to store the configuration data, a network configurer to retrieve the configuration data from the memory and to configure the network interface based on the retrieved data, and a power source other than the antenna to provide power to the memory and the network configurer during operation of the network configurer.
Abstract translation: 描述了配置嵌入式设备的系统，方法和设备。 一种示例性设备包括用于将设备与网络通信地耦合的网络接口，用于接收射频信号的天线，包括1）配置数据和2）功率，耦合到天线的存储器以接收电力并存储配置数据 ，网络配置器，用于从存储器检索配置数据，并且基于检索的数据配置网络接口，以及除了天线之外的电源，以在网络配置器的操作期间向存储器和网络配置器提供电力。
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公开(公告)号：US20160299558A1
公开(公告)日：2016-10-13
申请号：US15134756
申请日：2016-04-21
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US10095520B2
公开(公告)日：2018-10-09
申请号：US15194558
申请日：2016-06-27
Applicant: Intel Corporation
Inventor： Zhen Fang , Xiaowei Jiang , Srihari Makineni , Rameshkumar G. Illikkal , Ravishankar Iyer
Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
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公开(公告)号：US09870047B2
公开(公告)日：2018-01-16
申请号：US15192134
申请日：2016-06-24
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
CPC classification number: G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F9/4418 , G06F9/5094 , G06F12/084 , G06F13/24 , G06F2212/1028 , G06F2212/60 , G06F2212/62 , H04W52/028 , H04W88/02 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/22 , Y02D70/00
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US09128842B2
公开(公告)日：2015-09-08
申请号：US13631625
申请日：2012-09-28
Applicant: Intel Corporation
Inventor： Jaideep Moses , Ravishankar Iyer , Rameshkumar G. Illikkal , Sadagopan Srinivasan
CPC classification number: G06F12/08 , G06F12/0891
Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
Abstract translation: 描述了具有高速缓存电路和逻辑电路的处理器。 逻辑电路是管理高速缓存线路的高速缓存行的输入和移除。 逻辑电路包括存储电路和控制电路。 存储电路用于存储标识高速缓存中处于修改状态的一组高速缓存行的信息。 控制电路耦合到存储电路，以响应于刷新高速缓存的信号从存储电路接收信息，并从其中确定高速缓存的地址，从而从高速缓存读取高速缓存行集合，以避免 从缓存中读取处于无效或干净状态的缓存行。
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公开(公告)号：US10664039B2
公开(公告)日：2020-05-26
申请号：US16043738
申请日：2018-07-24
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC: G06F1/3293 , G06F9/50 , G06F1/3287 , G06F9/4401 , G06F13/24 , H04W52/02 , H04W88/02 , G06F1/3206 , G06F12/084
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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公开(公告)号：US20180329478A1
公开(公告)日：2018-11-15
申请号：US16043738
申请日：2018-07-24
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
IPC: G06F1/32 , H04W88/02 , H04W52/02 , G06F12/084 , G06F9/4401 , G06F9/50 , G06F13/24
Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
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9.发明申请公开(公告)号：US20160132354A1
公开(公告)日：2016-05-12
申请号：US14995198
申请日：2016-01-13
Applicant: Intel Corporation
Inventor： Ravishankar Iyer , Sadagopan Srinivasan , LI ZHAO , Rameshkumar G. Illikkal
CPC classification number: G06F9/4881 , G06F9/5027 , G06F11/3409 , G06F11/3433 , G06F12/084 , G06F2201/88 , G06N5/02 , Y02D10/13 , Y02D10/22 , Y02D10/34
Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
Abstract translation: 描述了在异构多处理器计算平台中调度应用程序的方法和装置。 在一个实施例中，处理器的多个处理器核的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。 处理器中的逻辑根据存储的信息确定哪个处理器内核应该执行应用程序。 还要求和公开其它实施例。
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公开(公告)号：US08861847B2
公开(公告)日：2014-10-14
申请号：US13724150
申请日：2012-12-21
Applicant: Intel Corporation
CPC classification number: G06K9/4652 , G06K9/00375
Abstract: A system and method for detecting human skin tone in one or more images. The system includes an image processing module configured to receive an image and provide contrast enhancement of the image so as to compensate for background illumination in the image. The image processing module is further configured to detect and identify regions of the contrast-enhanced image containing human skin tone based, at least in part, on the utilization of multiple color spaces and adaptively generated thresholds for each color space. A system and method consistent with the present disclosure is configure to provide accurate detection of human skin tone while accounting for variations in skin appearance due to a variety of factors, including background illumination and objects.
Abstract translation: 一种用于在一个或多个图像中检测人肤色调的系统和方法。 该系统包括被配置为接收图像并且提供图像的对比度增强以便补偿图像中的背景照明的图像处理模块。 图像处理模块还被配置为至少部分地基于多个颜色空间的利用和针对每个颜色空间的自适应生成的阈值来检测和识别包含人肤色的对比度增强图像的区域。 与本公开一致的系统和方法被配置为提供对人肤色调的准确检测，同时考虑到由于各种因素（包括背景照明和物体）引起的皮肤外观的变化。
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