公开(公告)号：US20250125260A1

公开(公告)日：2025-04-17

申请号：US18999945

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10D30/69 ,  H10D84/83

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20190318959A1

公开(公告)日：2019-10-17

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20160351449A1

公开(公告)日：2016-12-01

申请号：US15237542

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Rami HOURANI ,  Eungnak HAN ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：US20230369222A1

公开(公告)日：2023-11-16

申请号：US17743933

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Robert L. BRISTOL

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/823475 ,  H01L29/66742 ,  H01L29/66439

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer. The conductive feedthrough structure is a monolithic structure extending through the device layer.

公开(公告)号：US20220130719A1

公开(公告)日：2022-04-28

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20210082800A1

公开(公告)日：2021-03-18

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20210005511A1

公开(公告)日：2021-01-07

申请号：US17025087

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US20180294167A1

公开(公告)日：2018-10-11

申请号：US15769017

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  James M. BLACKWELL

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3105

Abstract: Described herein are structures and methods for preparing photobuckets for lithography, e.g. photolithography or electron-beam lithography. One method includes arranging photobuckets on a material to be etched using lithography and providing a layer of a first material at least on inner side walls of the photobuckets, followed by filling the photobuckets with a second material. The second material is more lithosensitive than the first material and the first material could be not lithosensitive at all. Layering each photobucket from the inner side wall(s) of the photobucket towards the center of the photobucket with materials that are increasingly more lithosensitive results in an improved control of lithographic patterning by reducing or eliminating edge placement errors of accidentally exposing photobuckets that should not have been exposed.

公开(公告)号：US20230369221A1

公开(公告)日：2023-11-16

申请号：US17743899

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Richard H. LIVENGOOD ,  Mauro J. KOBRINSKY ,  Robert L. BRISTOL ,  Akshit PEER

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L21/768

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L21/76898

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.

公开(公告)号：US20230369211A1

公开(公告)日：2023-11-16

申请号：US17743954

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： Clifford J. ENGEL ,  Robert L. BRISTOL ,  Richard H. LIVENGOOD ,  Ilan RONEN ,  Kevin Lai LIN

IPC: H01L23/528

CPC classification number: H01L23/5283

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive structures along corresponding ones of a plurality of line tracks along a first direction. The integrated circuit structure also includes a white space track included within the plurality of line tracks, the white space track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction. A conductive structure is along the white space track.