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    ENUMERATED PER DEVICE ADDRESSABILITY FOR MEMORY SUBSYSTEMS
    2.
    发明申请
    ENUMERATED PER DEVICE ADDRESSABILITY FOR MEMORY SUBSYSTEMS 审中-公开

    公开(公告)号：US20190042498A1

    公开(公告)日：2019-02-07

    申请号：US15987854

    申请日：2018-05-23

    Applicant: Intel Corporation

    Inventor： Tonia G. MORRIS ,  Bill NALE

    IPC: G06F13/16 ,  G06F3/06 ,  G06F9/30

    Abstract: A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

    REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRAINING PROCESS
    4.
    发明申请
    REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRAINING PROCESS 审中-公开

    公开(公告)号：US20190095308A1

    公开(公告)日：2019-03-28

    申请号：US15716460

    申请日：2017-09-26

    Applicant: Intel Corporation

    Inventor： Tonia G. MORRIS

    IPC: G06F11/34 ,  G06F11/30

    Abstract: A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.

    REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRAINING PROCESS
    6.
    发明申请
    REGISTERING CLOCK DRIVER CONTROLLED DECISION FEEDBACK EQUALIZER TRAINING PROCESS 审中-公开

    公开(公告)号：US20200334121A1

    公开(公告)日：2020-10-22

    申请号：US16919649

    申请日：2020-07-02

    Applicant: Intel Corporation

    Inventor： Tonia G. MORRIS

    IPC: G06F11/34 ,  G06F11/30 ,  G11C29/02

    Abstract: A method is described. The method includes receiving from a memory controller configuration information for a testing sequence and storing the configuration information in configuration register space of the driver circuit. The method also includes controlling the next testing sequence. The testing sequence includes sweeping values of a tap coefficient of a DFE circuit of the driver circuit and sweeping a voltage of a slicer of the driver circuit. The method includes sending results of the testing sequence to the memory controller. The results are to determine a value for the DFE tap coefficient.

    TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICES
    9.
    发明申请
    TRAINING FOR CHIP SELECT SIGNAL READ OPERATIONS BY MEMORY DEVICES 有权

    公开(公告)号：US20220148639A1

    公开(公告)日：2022-05-12

    申请号：US17441667

    申请日：2019-05-24

    Applicant: Intel Corporation

    Inventor： Zhenglong WU ,  Tonia G. MORRIS ,  Christina JUE ,  Daniel BECERRA PEREZ ,  David G. ELLIS

    IPC: G11C11/4076 ,  G11C11/4096

    Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

    MEMORY BUS MR REGISTER PROGRAMMING PROCESS
    10.
    发明申请
    MEMORY BUS MR REGISTER PROGRAMMING PROCESS 审中-公开

    公开(公告)号：US20200065266A1

    公开(公告)日：2020-02-27

    申请号：US16529700

    申请日：2019-08-01

    Applicant: Intel Corporation

    Inventor： Tonia G. MORRIS ,  John V. LOVELACE ,  John R. GOLES

    IPC: G06F13/16 ,  G06F1/10

    Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

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