公开(公告)号：US20150113234A1

公开(公告)日：2015-04-23

申请号：US14580976

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F3/06

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US20150325281A1

公开(公告)日：2015-11-12

申请号：US14639025

申请日：2015-03-04

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  John V. LOVELACE ,  Benjamin T. TYSON

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A memory controller transmits a control signal to a memory module, where the memory controller continuously transmits a clock signal to the memory module. The memory controller determines adjustments to the control signal with respect to the clock signal, by iteratively analyzing a strobe signal.

Abstract translation: 存储器控制器将控制信号发送到存储器模块，其中存储器控制器将时钟信号连续发送到存储器模块。 存储器控制器通过迭代地分析选通信号来确定相对于时钟信号对控制信号的调整。

公开(公告)号：US20160210187A1

公开(公告)日：2016-07-21

申请号：US15080577

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jonathan C. JASPER ,  Murugasamy K. NACHIMUTHU ,  Jun ZHU ,  Tuan M. QUACH

IPC: G06F11/07

Abstract: Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

Abstract translation: 提供了一种用于使用误差信号执行错误处理操作的方法和装置。第一错误信号在总线上的错误引脚上被断言，以向主机存储器控制器通知响应于检测到的存储器模块控制器执行错误处理操作 一个错误。 执行错误处理操作以响应于检测到错误将总线返回到初始状态。 在总线上的错误引脚上断言第二个错误信号，表示错误处理操作已经完成，总线返回初始状态。

公开(公告)号：US20150095565A1

公开(公告)日：2015-04-02

申请号：US14040548

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US20170286330A1

公开(公告)日：2017-10-05

申请号：US15624702

申请日：2017-06-15

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/4096 ,  G06F13/42 ,  G06F3/06 ,  G11C11/4093

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US20150113235A1

公开(公告)日：2015-04-23

申请号：US14581011

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F3/06

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

公开(公告)号：US20170031846A1

公开(公告)日：2017-02-02

申请号：US15294671

申请日：2016-10-14

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F13/16 ,  G11C11/4096 ,  G11C11/4093 ,  G06F13/40

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。

公开(公告)号：US20160211973A1

公开(公告)日：2016-07-21

申请号：US15080580

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jonathan C. JASPER ,  Jun ZHU ,  Tuan M. QUACH

IPC: H04L9/08 ,  G06F13/16 ,  G11C7/10 ,  G06F13/42

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus method and apparatus for scrambling read data in a memory module. A read data packet having scrambled read data returned in response to a read request is received. The scrambler seed is updated in response to receiving the read data packet. The scrambler seed is used to descramble the scrambled read data.

Abstract translation: 提供了一种用于扰乱存储器模块中的读取数据的方法和装置方法和装置。 接收到响应读取请求返回的具有加扰读取数据的读取数据分组。 响应于接收到读取的数据分组来更新加扰器种子。 加扰器种子用于解扰加扰的读取数据。

公开(公告)号：US20150113215A1

公开(公告)日：2015-04-23

申请号：US14580869

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Tonia G. MORRIS ,  Jonathan C. JASPER ,  Arnaud J. FORESTIER

IPC: G06F13/42 ,  G11C7/10

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4234 ,  G11C11/4093 ,  G11C11/4096

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract translation: 提供了一种用于对存储器模块进行编程以启动训练模式的装置和计算机可读存储介质，其中存储器模块在总线接口的边带通道上发送连续位模式; 通过总线接口接收位模式; 从接收到的位模式确定位模式中的值的转变以确定所确定的值的转换之间的数据眼; 以及确定设置以控制相位内插器以产生用于对所确定的数据眼睛内的数据进行采样的内插信号。