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公开(公告)号：US08476141B2
公开(公告)日：2013-07-02
申请号：US13737785
申请日：2013-01-09
Applicant: Intermolecular, Inc. , Elpida Memory, Inc.
Inventor： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号：US20130143384A1
公开(公告)日：2013-06-06
申请号：US13737785
申请日：2013-01-09
Applicant: INTERMOLECULAR, INC. , ELPIDA MEMORY, INC
Inventor： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC: H01L49/02
Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号：US20150087130A1
公开(公告)日：2015-03-26
申请号：US14033326
申请日：2013-09-20
Applicant: Elpida Memory, Inc , Intermolecular, Inc.
Inventor： Hanhong Chen , David Chi , Imran Hashim , Mitsuhiro Horikawa , Sandra G. Malhotra
IPC: H01L49/02
CPC classification number: H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
Abstract translation: 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。
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公开(公告)号：US20140187015A1
公开(公告)日：2014-07-03
申请号：US13727898
申请日：2012-12-27
Applicant: INTERMOLECULAR, INC. , ELPIDA MEMORY, INC.
Inventor： Xiangxin Rui , Mitsuhiro Horikawa , Hiroyuki Ode , Karthik Ramani
IPC: H01L49/02
Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.
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公开(公告)号：US20130217202A1
公开(公告)日：2013-08-22
申请号：US13830282
申请日：2013-03-14
Applicant: Intermolecular, Inc. , Elpida Memory, Inc.
Inventor： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
IPC: H01L49/02
Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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Patent Agency Ranking
公开(公告)号：US08969169B1
公开(公告)日：2015-03-03
申请号：US14033326
申请日：2013-09-20
Applicant: Intermolecular, Inc. , Elpida Memory, Inc
Inventor： Hanhong Chen , David Chi , Imran Hashim , Mitsuhiro Horikawa , Sandra G. Malhotra
CPC classification number: H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
Abstract translation: 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。
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公开(公告)号：US08815695B2
公开(公告)日：2014-08-26
申请号：US13727898
申请日：2012-12-27
Applicant: Intermolecular, Inc. , Elpida Memory, Inc
Inventor： Xiangxin Rui , Mitsuhiro Horikawa , Hiroyuki Ode , Karthik Ramani
IPC: H01L21/02 , H01L27/108 , H01L29/92 , H01L21/8242 , H01L21/316 , H01L27/04 , H01L49/02
Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.
Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。
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公开(公告)号：US08541283B2
公开(公告)日：2013-09-24
申请号：US13830282
申请日：2013-03-14
Applicant: Intermolecular, Inc. , Elpida Memory, Inc
Inventor： Sandra G. Malhotra , Hanhong Chen , Wim Y. Deweerd , Mitsuhiro Horikawa , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui
Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.
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公开(公告)号：US09281357B2
公开(公告)日：2016-03-08
申请号：US14599843
申请日：2015-01-19
Applicant: Intermolecular, Inc. , Elpida Memory, Inc
Inventor： Hanhong Chen , David Chi , Imran Hashim , Mitsuhiro Horikawa , Sandra G. Malhotra
IPC: H01L49/02 , H01L27/108
CPC classification number: H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
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公开(公告)号：US20150137315A1
公开(公告)日：2015-05-21
申请号：US14599843
申请日：2015-01-19
Applicant: Intermolecular, Inc. , Elpida Memory, Inc.
Inventor： Hanhong Chen , David Chi , Imran Hashim , Mitsuhiro Horikawa , Sandra G. Malhotra
IPC: H01L49/02 , H01L27/108
CPC classification number: H01L28/56 , H01L27/108 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/82
Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.
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