公开(公告)号：US20180261710A1

公开(公告)日：2018-09-13

申请号：US15976308

申请日：2018-05-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JEEHWAN KIM ,  DAVID B. MITZI ,  BYUNGHA SHIN ,  TEODOR K. TODOROV ,  MARK T. WINKLER

IPC: H01L31/0749 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/072 ,  H01L31/032

CPC classification number: H01L31/0749 ,  H01L31/02167 ,  H01L31/0326 ,  H01L31/072 ,  H01L31/18 ,  H01L31/1868 ,  Y02E10/50

Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.

公开(公告)号：US20180261711A1

公开(公告)日：2018-09-13

申请号：US15976331

申请日：2018-05-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JEEHWAN KIM ,  DAVID B. MITZI ,  BYUNGHA SHIN ,  TEODOR K. TODOROV ,  MARK T. WINKLER

IPC: H01L31/0749 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/072 ,  H01L31/032

CPC classification number: H01L31/0749 ,  H01L31/02167 ,  H01L31/0326 ,  H01L31/072 ,  H01L31/18 ,  H01L31/1868 ,  Y02E10/50

Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.

公开(公告)号：US20150263087A1

公开(公告)日：2015-09-17

申请号：US14726104

申请日：2015-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHRISTOS D. DIMITRAKOPOULOS ,  JEEHWAN KIM ,  HONGSIK PARK ,  BYUNGHA SHIN

IPC: H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  C30B25/18 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02664 ,  H01L21/304 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/127 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/32 ,  Y10T156/1082

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract translation: 一种用于形成纳米结构的方法包括将柔性基板结合到具有形成在与柔性基板相对的一侧上的二维材料的晶体半导体层。 晶体半导体层在第一方向上受到应力以引发晶体半导体层中的第一裂纹。 第一裂纹通过晶体半导体层和二维材料传播。 释放晶体半导体层的应力以提供包括晶体半导体层上的二维材料的平行结构。

公开(公告)号：US20160204196A1

公开(公告)日：2016-07-14

申请号：US15077213

申请日：2016-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHRISTOS D. DIMITRAKOPOULOS ,  JEEHWAN KIM ,  HONGSIK PARK ,  BYUNGHA SHIN

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/32 ,  H01L29/12

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  C30B25/18 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02664 ,  H01L21/304 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/127 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/32 ,  Y10T156/1082

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

公开(公告)号：US20150340536A1

公开(公告)日：2015-11-26

申请号：US14819007

申请日：2015-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： JEEHWAN KIM ,  DAVID B. MITZI ,  BYUNGHA SHIN ,  TEODOR K. TODOROV ,  MARK T. WINKLER

IPC: H01L31/0749 ,  H01L31/0216 ,  H01L31/18

CPC classification number: H01L31/0749 ,  H01L31/02167 ,  H01L31/0326 ,  H01L31/072 ,  H01L31/18 ,  H01L31/1868 ,  Y02E10/50

Abstract: A photovoltaic device and method include a substrate, a conductive layer formed on the substrate and an absorber layer formed on the conductive layer from a Cu—Zn—Sn containing chalcogenide material. An emitter layer is formed on the absorber layer and a buffer layer is formed on the emitter layer including an atomic layer deposition (ALD) layer. A transparent conductor layer is formed on the buffer layer.

Abstract translation: 光电器件和方法包括：衬底，形成在衬底上的导电层和由含有Cu-Zn-Sn的硫族化物材料形成在导电层上的吸收层。 在吸收层上形成发射极层，在包括原子层沉积（ALD）层的发射极层上形成缓冲层。 在缓冲层上形成透明导体层。

公开(公告)号：US20150235849A1

公开(公告)日：2015-08-20

申请号：US14701213

申请日：2015-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHRISTOS D. DIMITRAKOPOULOS ,  JEEHWAN KIM ,  HONGSIK PARK ,  BYUNGHA SHIN

IPC: H01L21/02 ,  H01L21/304

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  C30B25/18 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02664 ,  H01L21/304 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/127 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/32 ,  Y10T156/1082

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.