公开(公告)号：US09853116B2

公开(公告)日：2017-12-26

申请号：US14968471

申请日：2015-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J. Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

公开(公告)号：US20140217481A1

公开(公告)日：2014-08-07

申请号：US13757809

申请日：2013-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J. Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections: a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers; source and drain regions; a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer; an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation; and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

Abstract translation: 半导体器件中的栅极结构包括：形成在具有三个部分的基底上的栅极堆叠：顶部上的底部，顶部和牺牲帽层; 门间隔; 源和漏区; 在除去牺牲帽层之后，在栅极堆叠的顶部和侧壁上的氮化物封装; 在氮化物封装之上的有机平面化层，平坦化封装; 并且在除去氮化物封装，有机平坦化层和栅极堆叠的顶部之后在源极和漏极区域和底部部分上进行硅化。

公开(公告)号：US20150044843A1

公开(公告)日：2015-02-12

申请号：US14489699

申请日：2014-09-18

Applicant: International Business Machines Corporation

Inventor： Michael V. Aquilino ,  Daniel J. Jaeger ,  Reinaldo A. Vega

IPC: H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76281 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76208 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

Abstract translation: 提供了包括第一外延半导体层的半导体衬底。 第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。 包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。 包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。 至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。 第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

公开(公告)号：US08629028B2

公开(公告)日：2014-01-14

申请号：US13773881

申请日：2013-02-22

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC: H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

公开(公告)号：US20160099332A1

公开(公告)日：2016-04-07

申请号：US14968471

申请日：2015-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dechao Guo ,  Wilfried E. Haensch ,  Shu-jen Han ,  Daniel J. Jaeger ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/4925 ,  H01L21/28052 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.

公开(公告)号：US20130337624A1

公开(公告)日：2013-12-19

申请号：US13773881

申请日：2013-02-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

公开(公告)号：US20130140670A1

公开(公告)日：2013-06-06

申请号：US13759429

申请日：2013-02-05

Applicant: International Business Machines Corporation

Inventor： Michael V. Aquilino ,  Christopher V. Baiocco ,  Richard A. Conti ,  Daniel J. Jaeger ,  Vijay Narayanan

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/517

Abstract: A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

Abstract translation: 提供基板。 在衬底中形成STI沟槽。 填充材料形成在STI沟槽中，然后平坦化。 将衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。 衬垫降低了高k金属栅极器件中的Vt-W效应。